Patterned silicon-on-insulator layers and methods for...
PECVD air gap integration
Planarized and fill biased integrated circuit chip
Planarized deep-shallow trench isolation for CMOS/bipolar device
Planarized isolation structure for CMOS devices
Planarized local oxidation by trench-around technology
Planarized semiconductor structure using subminimum features
Planarized semiconductor structure with subminimum features
Plating a conductive material on a dielectric material
Poly-buffered LOCOS process
Polysilicon coated nitride-lined shallow trench
Porous low-k dielectric interconnects with improved adhesion...
Post passivation interconnection schemes on top of IC chip
Power semiconductor component
Power semiconductor component having a PN junction with a...
Power semiconductor device
Power transistor cell
Power transistor with internally combined low-pass and...
Process for fabricating doped zinc oxide microsphere gel
Process for fabricating semiconductor device including improved