Planarized semiconductor structure with subminimum features

Details Planarized semiconductor structure with subminimum features Planarized semiconductor structure with subminimum features

1995-06-06

1996-07-23

Brown, Peter Toby

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257754, 257755, 257757, 257773, 257734, 257752, H01L 2350

Patent

active

055392407

ABSTRACT:
Improved, planarized semiconductor structures are described which are prepared by a method involving the creation of a series of subminimum (i.e., 50 to 500 angstroms thick) polysilicon pillars extending vertically upward from the base of a wide trench and depositing a conductor material by chemical vapor deposition over the pillars; the pillars prevent the formation of a depression within the trench when planarized.

REFERENCES:
patent: 4139442 (1979-02-01), Bondur et al.
patent: 4493740 (1985-01-01), Komeda
patent: 4887144 (1989-12-01), Cook et al.
patent: 4944836 (1990-07-01), Beyer et al.
patent: 4982266 (1991-01-01), Chatterjee
patent: 5094973 (1992-03-01), Pang
patent: 5191509 (1993-03-01), Wen
patent: 5204280 (1993-04-01), Dhong et al.
Patent Abstracts of Japan, vol. 9 No. 126 (E-318) [ 1849]May 31, 1985; Japan Kokai #60-015944.

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