Porous low-k dielectric interconnects with improved adhesion...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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Details

C257S506000, C257S507000, C257S524000

Reexamination Certificate

active

06933586

ABSTRACT:
An electrical interconnect structure on a substrate, includes a first porous dielectric layer with surface region from which a porogen has been removed; and an etch stop layer disposed upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed, thus improving adhesion during subsequent processing. The porogen may be removed from the surface region by heating, and in particular by hot plate baking. A second porous dielectric layer, which may have the same composition as the first porous dielectric layer, may be formed over the etch stop layer. Electrical vias and lines may be formed in the first and second porous dielectric layer, respectively. The layers may be part of a multilayer stack, wherein all of the layers are cured simultaneously in a spin application tool porous dielectric layer.

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patent: WO 00/31183 (2000-06-01), None
patent: WO 00/40637 (2000-07-01), None

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