Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-06-18
2003-10-21
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S367000, C257S544000
Reexamination Certificate
active
06635944
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a power semiconductor component having a pn junction and an associated edge termination.
A pn junction which has a high blocking capability and, in the vertical direction, takes up a potential difference to be blocked, which pn junction extends (planar pn junction) only over a limited region of a semiconductor body, e.g. a monocrystalline silicon substrate, requires an edge termination structure in order to attain the dielectric strength. This edge termination structure is provided for the purpose of rotating the course of the electric field from a vertical orientation in the central region of the component to a horizontal course, i.e. parallel to the top side of the chip, in the edge region. Moreover, there must be a region of the chip surface present in which the electric field can emerge from the chip into the surroundings. In this case, the maximum dielectric strength of the pn junction in the planar central region, which is provided for the actual voltage blocking, should be reduced as little as possible by effects caused by the curvature of the area of the pn junction at the edge. Moreover, the region where the electric field emerges from the chip should be as small as possible. With known edge termination constructions, which usually comprise a suitable combination of differently doped regions and conductive field plates arranged above the latter, a width of the emergence region which is given by the quotient of required dielectric strength and breakdown field strength of silicon (2*10
5
V/cm) cannot, in principle, be undershot. Such edge terminations are described e.g. in U.S. Pat. No. 4,672,738, U.S. Pat. No. 4,757,031 and U.S. Pat. No. 5,113,237.
SUMMARY OF THE INVENTION
It is an object of the present invention to specify a component which is suitable for power applications and has an edge termination of a pn junction which requires the least possible chip area.
The component according to the invention has an edge structure by means of which the area requirement for the emergence of the electric field at the top side of the chip is significantly smaller than would be allowed by the breakdown field strength of the semiconductor material, in particular silicon. This is achieved by virtue of the fact that a dielectric incorporated in the semiconductor body and having a distinctly higher breakdown field strength than silicon deflects the electric field within the semiconductor body in such a way that the equipotential areas essentially run vertically to the top side of the chip through said dielectric. The electric field is therefore diverted by the central region of the component, in which the equipotential areas essentially run in a coplanar manner with respect to the top side of the chip, from the vertical direction in a horizontal direction with regard to the top side of the chip, which occurs over a comparatively short distance within the dielectric. In the region where the electric field emerges from the chip, the essential part of the field is situated in the dielectric. As a result, the area requirement is essentially limited to the surface region of the dielectric.
REFERENCES:
patent: 4672738 (1987-06-01), Stengl et al.
patent: 4757031 (1988-07-01), Kuhnert et al.
patent: 5113237 (1992-05-01), Stengl
patent: 19858762.7 (1998-12-01), None
Greenberg Laurence A.
Infineon - Technologies AG
Lewis Monica
Locher Ralph E.
Meier Stephen D.
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