Planarized semiconductor structure using subminimum features

Details Planarized semiconductor structure using subminimum features Planarized semiconductor structure using subminimum features

1993-10-27

1995-09-26

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257513, 257520, H01L 21469

Patent

active

054536391

ABSTRACT:
Improved, planarized semiconductor structures are described. They are prepared by a method which involves the creation of a series of subminimum (i.e., 50 to 500 Angstroms thick) silicon pillars extending vertically upward from the base of a wide trench, and oxidizing the pillars. When the substrate is covered with a conformal CVD oxide, the pillars prevent the formation of a single deep depression above the trench.

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