Planarized isolation structure for CMOS devices

Details Planarized isolation structure for CMOS devices Planarized isolation structure for CMOS devices

1994-07-15

1995-08-08

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

257510, 257634, H01L 21473

Patent

active

054401666

ABSTRACT:
A field oxide structure is formed within a cavity formed in a semiconductor substrate. The cavity has a U-shaped cross section. A layer of thermal oxide covers the walls and bottom of the cavity, and a region of reflowable glass or spin on glass fills the cavity. A layer of undoped oxide, having an upper surface coplanar with the substrate upper surface is formed over the cavity, so that the spin on or reflowable glass is completely surrounded by either thermal oxide or an undoped oxide layer.

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patent: 5128743 (1992-07-01), Tamaki et al.
patent: 5221857 (1993-06-01), Kano
S. M. Sze, Semiconductor Devices/Phys. & Tech., Part of Chapter 9, Oxidation & Film Dep. pp. 341-363, 1985.

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