CMOS structure having dynamic threshold voltage

CMOS structure with FETS having isolated wells with merged deple

CMOS structure with parasitic channel prevention

CMOS structure with varying gate oxide thickness and with both d

CMOS substrate biasing for threshold voltage control

CMOS thin film transistor comprising common gate, logic...

CMOS transistor

CMOS transistor and isolated back gate electrodes on an SOI subs

CMOS transistor and method of manufacturing the same

CMOS transistor and method of manufacturing the same

CMOS transistor design for shared N+/P+ electrode...

CMOS transistor having different PMOS and NMOS gate...

CMOS transistor having different PMOS and NMOS gate...

CMOS transistor junction regions formed by a CVD etching and...

CMOS transistor structure including film having reduced...

CMOS transistor with two-layer inverse-T tungsten gate

CMOS transistors using gate electrodes to increase channel...

CMOS transistors with differential oxygen content high-K...

CMOS transistors with self-aligned planarization twin-well by us

CMOS type solid imaging device