CMOS substrate biasing for threshold voltage control

Details CMOS substrate biasing for threshold voltage control CMOS substrate biasing for threshold voltage control

1996-06-14

1998-11-17

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257371, 257901, 257350, 326 33, 326 34, 327537, H01L 27092

Patent

active

058380477

ABSTRACT:
A semiconductor device includes a PMOS transistor and an NMOS transistor. In a standby state, a potential of Vcc level is applied to the substrate of the PMOS transistor and a potential of Vss level is applied to the substrate of the NMOS transistor. Therefore, the voltage between the source and substrate of the P and NMOS transistors becomes 0 V. In an active state, potentials that render the voltage between the source and substrate lower than the built-in potential are applied to respective substrates of the P and NMOS transistors. Therefore, the threshold voltage of the transistor is lowered in an active state than in a standby state, and almost no leakage current flows between the source and substrate.

REFERENCES:
patent: 5557231 (1996-09-01), Yamaguchi et al.
patent: 5610533 (1997-03-01), Arimoto et al.
Daisaburo Takashima et al, Stand-by/Active Mode Logic for Sub-1 V 1G/4Gb DRAMs, VLSI Circuit Symp. 1993, pp. 83-84.

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