CMOS transistor with two-layer inverse-T tungsten gate

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257382, 257384, 257388, 257412, 257764, 257768, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

056335229

ABSTRACT:
The present invention is directed to a unique silicon based MOS transistor having an inverse-T refractory metal gate structure. The gate fabricated according to this invention comprises a main CVD tungsten portion and a lower sputtered tungsten portion outwardly extending from the bottom of the CVD portion such that a cross section of the gate appears as an inverted "T". A Cl.sub.2 /O.sub.2 plasma etch is used to etch the CVD tungsten layer and a chemical etch is used to etch the sputtered tungsten layer to form the gate electrode. It has been discovered that sputtered tungsten is more resistant to Cl.sub.2 /O.sub.2 reactive ion etch than is CVD tungsten. The sputtered tungsten layer acts as a shield to protect the underlying gate oxide layer from ion damage throughout the fabrication process.

REFERENCES:
patent: 4356623 (1982-11-01), Hunter
patent: 4478678 (1984-10-01), Watanabe
patent: 4672419 (1987-06-01), McDavid
patent: 4901128 (1990-02-01), Sanami et al.
patent: 4906589 (1990-03-01), Chao
patent: 4963504 (1990-10-01), Huang
patent: 4984042 (1991-01-01), Pfiester et al.
patent: 5097301 (1992-03-01), Sanchez
patent: 5140403 (1992-08-01), Hikichi et al.
patent: 5162884 (1992-11-01), Liou et al.
patent: 5182619 (1993-01-01), Pfiester
"High Resolution Tungsten Patterning Using Buffered, Mildly Basic Etching Solutions"; T. A. Shankoff et al.; Bell Laboratories; Murray Hill, NJ; pp. 294-297; vol. 122, No. 2.
"Metal Vapor Effects on Chemical Reactions in an Argon Plasma"; Paul Meubus; Universite du Quebec a Chicoutimi; Quebec, Canada; Dept. of Applied Sciences; J. electrochem. Soc.; Feb. 1975; p. 298.
"Composite Refractory metal Gate Elecrtrodes for High Speed NMOS and CMOS FET"; IBM Technical Disclosure Bulletin 30 (1987); Dec., No. 7.
"Two Step Deposition Method for Reducing Surface States of Mo Gate MOS Devices With Thin Gate Oxides"; T. Amazawa et al.; 2419 Japanese Journal of Applied Physics. Supplements 1983); 15th Conf., Tokyo, Japan; pp. 229-232.
"Effect of W Film Stress on W-Gate MOS Characteristics"; Hideaki Matsuhashi et al.; 2419 Japanese Journal of applied Physics (1989) 28-30 Aug.; 21st Conf.; Tokyo, Japan; pp. 17-20.
T.A. Shankoff et al., High Resolution Tugnsten Patterning Using Buffered, Mildly Basic Etching Solutions, J. Electrochem. Soc. (1975).
James R. Pfiester et al., A Selectively Deposited Poly-Gate ITLDD Process with Self-Aligned LDD/Channel Implantation, IEEE 1990.
Tiao-yuan Huang et al., A Novel Submicron LDD Transistor With Inverse-T Gate Structure, 1986 IEEE.
Naoki Kasai et al., Deep-Submicron Tungsten Gate CMOS Technology, 1988 IEEE.
C.Y. Ting et al., Gate Materials Consideration for Submicron CMOS, Applied Surface Science 38 (1989) 416-427.
N. Kobayashi et al., Highly Reliable Tungsten Gate Technology, 1987 Materials Research Society.

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