Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2008-10-13
2010-10-12
Le, Dung A. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S338000, C257S344000, C257S345000, C257SE21106
Reexamination Certificate
active
07812394
ABSTRACT:
This invention adds to the art of replacement source-drain cMOS transistors. Processes may involve etching a recess in the substrate material using one equipment set, then performing deposition in another. Disclosed is a method to perform the etch and subsequent deposition in the same reactor without atmospheric exposure. In-situ etching of the source-drain recess for replacement source-drain applications provides several advantages over state of the art ex-situ etching. Transistor drive current is improved by: (1) Eliminating contamination of the silicon-epilayer interface when the as-etched surface is exposed to atmosphere and (2) Precise control over the shape of the etch recess. Deposition may be done by a variety of techniques including selective and non-selective methods. In the case of blanket deposition, a measure to avoid amorphous deposition in performance critical regions is also presented.
REFERENCES:
patent: 5620912 (1997-04-01), Hwang et al.
patent: 5710450 (1998-01-01), Chau et al.
patent: 6137149 (2000-10-01), Kodama
patent: 6214679 (2001-04-01), Murthy et al.
patent: 6323525 (2001-11-01), Noguchi et al.
patent: 6342421 (2002-01-01), Mitani et al.
patent: 6774000 (2004-08-01), Natzle et al.
patent: 2002/0048911 (2002-04-01), Nuttall et al.
patent: 2004/0248368 (2004-12-01), Natzle et al.
patent: 2004/0262683 (2004-12-01), Bohr et al.
patent: 07022338 (1995-01-01), None
patent: WO 00/30169 (2000-05-01), None
Loo, R. et al., “A new technique to fabricate ultra-shallow-junctions, combining in situ vapour HCI etching and in situ doped epitaxial SiGe re-growth”, Applied Surface Science, vol. 224., No. 1-4, Mar. 15, 2004, pp. 63-67.
Kah Wee Ang et al., “Enhanced performance in 50nm N-MOSFETS with silicon-carbon source/drain regions”, IEEE International Electron Devices Meeting, 2004. IEDM Technical Digest, San Francisco, CA, Dec. 13-15, 2004, pp. 1069-1071.
Ueno, T. et al., “Dramatically enhanced performance of recessed SiGe source-drain pmos by in-situ etch and regrowth technique (InSERT)”, VLSI Technology 2005, Digest of Technical Papers, 2005 Symposium on Kyoto, Japan, Jun. 14-16, 2005.
Zhikuan Zhang et al., “Self-aligned recessed source/drain ultra-thin body SOI MOSFET technology”, Proceeding of the 34th European Solid-State Device Research Conference, 2004. ESSDERC 2004, Leuven, Belgium, Sep. 21-23, 2004, pp. 301-304.
Glass Glenn A.
Hattendorf Michael L.
Murthy Anand
Wank Jeffrey R.
Westmeyer Andrew N.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Le Dung A.
LandOfFree
CMOS transistor junction regions formed by a CVD etching and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with CMOS transistor junction regions formed by a CVD etching and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS transistor junction regions formed by a CVD etching and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4178044