CMOS transistor design for shared N+/P+ electrode...

Details CMOS transistor design for shared N+/P+ electrode... CMOS transistor design for shared N+/P+ electrode...

1999-01-22

2001-06-26

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S385000, C257S371000, C257S351000

Reexamination Certificate

active

06252283

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to an integrated circuit with transistors, and to a method of making the same incorporating a shared doping scheme for transistors of different conductivity types.
2. Description of the Related Art
A typical field effect transistor implemented in silicon consists of a source and a drain formed in a silicon substrate, and separated laterally to define a channel region in the substrate. A gate electrode composed of a conducting material, such as aluminum or polysilicon, is disposed over the channel region and designed to emit an electric field into the channel region. Changes in the electric field emitted by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain.
In a conventional process flow for forming a typical field effect transistor, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon and the gate oxide are then anisotropically etched back to the upper surface of the substrate leaving a polysilicon gate electrode stacked on top of a gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed by implanting a dopant species into the substrate. The gate electrode acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode. Many conventional semiconductor fabrication processes employ a double implant process to form the source and drain. The first implant is performed self-aligned to the gate electrode to establish lightly doped drain (“LDD”) structures. After the LDD implant, dielectric sidewall spacers are formed adjacent to the gate electrode by depositing and anisotropically etching a dielectric material, such as silicon dioxide. The second of the two source/drain implants is then performed self-aligned to the sidewall spacers. The substrate is annealed to activate the dopant in the source and the drain. Salicidation steps frequently follow the formation of the source and drain.
Early MOS integrated circuits were implemented as p-channel enhancement mode devices using aluminum as the gate electrode material. Aluminum had the advantages of relatively low resistivity and material cost. Furthermore, there was already a large body of manufacturing experience with aluminum in the chip industry developed from bipolar integrated circuit processing.
A later process innovation that is still widely used today, involves the use of heavily doped polysilicon as a gate electrode material in place of aluminum. The switch to polysilicon as a gate electrode material was the result of certain disadvantages associated with aluminum in early fabrication technologies. In conventional semiconductor fabrication processing, aluminum must be deposited following completion of all high temperature process steps (including drive-in of the source and drain regions). As a result, an aluminum gate electrode must ordinarily be separately aligned to the source and drain. This alignment procedure can adversely affect both packing density and parasitic overlap capacitances between the gate and source/drain regions. In contrast, polysilicon with its much higher melting point, can be deposited prior to source and drain formation and therefore provide for self-aligned gate processing. Furthermore, the high temperature capability of polysilicon is routinely exploited to enable interlevel dielectric layers to be applied to provide multiple metallization layers with improved planarity.
Despite the several advantages of polysilicon over aluminum as a gate electrode material, polysilicon has the disadvantage of polysilicon depletion effects. In p-channel transistors, the source and drain are commonly formed in the substrate by implanting a p-type dopant, such as boron. The implant also deposits boron into the polysilicon of the gate electrode. Subsequent thermal processing steps to fabricate a conventional p-channel field effect transistor frequently cause boron to diffuse from the gate electrode through the gate oxide layer and into the channel region. If the amount of boron diffused is sufficiently high, the electrical performance of the field effect transistor may be severely degraded due to polysilicon depletion.
Another potential shortcoming of conventional gate electrode formation, particularly in CMOS circuits, is asymmetrical threshold voltages for n-channel and p-channel devices. For optimal logic gate performance, the threshold voltages of n-channel and p-channel devices in a CMOS circuit should have comparable magnitudes. In addition, it is desirable to keep threshold voltages for both types of devices as small as possible in order to minimize sub-threshold currents and needless power consumption. Conventional process flows have incorporated various combinations of n
+
or p
+
polysilicon gate electrodes for n-channel and p-channel devices. For n-channel devices incorporating n
+
polysilicon gate electrodes, the work function of n
+
polysilicon is ideal, and will yield threshold voltages of less than about 0.7 volts for common values of channel doping and oxide thicknesses. However, where n
+
polysilicon is used as the gate electrode for a p-channel device, proper control of threshold voltage is more difficult since the threshold voltage of the p-channel device is already more negative than −0.7 volts, particularly in the doping range of 10
15
to 10
17
cm
−3
.
A boron implant is commonly used to adjust the threshold voltage of p-channel as well as n-channel devices in CMOS circuits with n
+
polysilicon gates. This approach has been widely used in semiconductor processing but requires careful tailoring of the background dopings of the substrate and the well in view of the parameters for the threshold voltage control implant. The requisite tying of these various parameters represents processing complexity and a limitation on the flexibility of a given process flow.
Another approach in CMOS processing has involved a dual-doped polysilicon process in which n
+
polysilicon is used as the gate electrode material for n-channel devices and p
+
polysilicon is used as a gate electrode material for p-channel devices. Such a dual doped approach can lead to difficulties when interconnection is made between the n
+
and p
+
polysilicon gate electrodes, such as when the two transistors are used to construct an inverter. The interconnect between the n
+
and p
+
polysilicon gates is frequently made via a silicide local interconnect strap that provides a diffusion pathway for the p and n-type dopants of the two gates. During subsequent high temperature steps the migrating p and n-type dopants may counterdope the respective gate electrodes and significantly degrade the performance of the transistors.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, an integrated circuit is provided that includes a substrate and a plurality of transistors positioned thereon. Each of the plurality of transistors has a gate dielectric layer positioned on the substrate, a first source/drain region and a second source/drain region, and a gate electrode positioned on the gate dielectric layer. The gate electrode has a lower surface, a midpoint, a quantity of p-type impurity, a quantity of nitrogen having a peak concentration proximate the lower surface, and a quantity of germanium.
In accordance with another aspect of the present invention, an integrated circuit transistor on a substrate is provided that includes a gate dielectric layer positioned on the substrate, a first source/drain region and a second source/drain region. A gate electrode is positioned on the gate dielectric layer. The gate electrode has a lower surf

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