CMOS structure having dynamic threshold voltage

Details CMOS structure having dynamic threshold voltage CMOS structure having dynamic threshold voltage

2002-02-07

2002-10-15

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000

Reexamination Certificate

active

06465849

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90133087, filed Dec. 31, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a complementary metal oxide semiconductor (CMOS) structure having a dynamic threshold voltage. More particularly, the present invention relates to a CMOS structure having a dynamic threshold voltage capable of cutting off any parasitic diode.
2. Description of Related Art
A complementary metal oxide semiconductor (CMOS) structure consists of an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor. In the circuit design of a CMOS structure, the substrate of each MOS transistor is connected to a common bulk voltage.
FIG. 1
is a schematic cross-sectional view of the NMOS transistor in a conventional CMOS structure. In the NMOS transistor, a P
+
ion-implanted region
105
is coupled to a terminal having a bulk voltage (V
bulk
). According to conventional techniques, when the bias voltage of the substrate (the P-well)
109
relative to the N
+
ion-implanted region (source terminal)
101
or the N
+
ion-implanted region (drain terminal)
103
is a forward bias voltage, threshold voltage of the MOS transistor is lowered. Hence, the NMOS transistor has higher driving voltage. However, since the threshold is reduced, the leakage current will accordingly increase and a substrate voltage should be properly controlled, so as to avoid large forward diode current from substrate to source region.
To provide a lower threshold voltage to a CMOS structure, two major methods are frequently used. One technique is using an extra circuit to control the gate terminal and the substrate to have different voltages so that the forward bias voltage created by applying the voltage to the substrate causes a lowed threshold voltage. For the another technique, in a CMOS structure, both the gate terminal and the substrate use an identical voltage. Similarly, the forward bias voltage created by applying the voltage to the substrate causes a lowed threshold voltage. However, in the first case, because the gate terminal and the substrate have different voltages, extra circuit is required to control substrate bias voltage. Consequently, overall complexity of circuit design for channeling the extra circuit is increased. As to the second case, both the gate terminal and the substrate use an identical voltage. Hence, the use of the gate voltage (V
G
) is restricted by the operation voltage of the diode (about 0.6 V). Ultimately, there is a limit to the operation voltage.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a complementary metal oxide semiconductor (CMOS) structure having a dynamic threshold voltage. The CMOS structure includes a metal oxide semiconductor (MOS) transistor, a first diode and a second diode. A first terminal of the first diode is coupled to the gate terminal of the MOS transistor and a second terminal of the first diode is coupled to the substrate of the MOS transistor. A first terminal of the second diode is coupled to the bulk voltage and a second terminal of the second diode is coupled to the substrate of the MOS transistor. The above structure is for NMOS devices. If the PMOS devices are used, the connection direction for the diodes is reversed.
This invention also provides a second CMOS structure having a dynamic threshold voltage. The second CMOS structure includes a substrate, a MOS transistor, a first ion-implanted region, an isolation layer, a second ion-implanted region and a third ion-implanted region. The substrate has a well region. The MOS transistor has source/drain regions and a gate terminal. The source/drain regions are embedded within the well region. The source/drain regions are doped using dopants that differ from the well. The gate terminal is located above a channel region between the drain region and the source region. The first ion-implanted region is within the well. The first ion-implanted region and the drain/source region are adjacent to each other except for the isolation layer between them. The first ion-implanted region is electrically connected to the gate terminal. The first ion-implanted region, the source region and the drain region are doped with identical types of ions. The second ion-implanted region is also within the well adjacent to the first ion-implanted region. However, the second ion-implanted region contains dopants that differ from the first ion-implanted region. The third ion-implanted region is also within the well but adjacent to the second ion-implanted region. The third ion-implanted region contains dopants identical to the ones in the first ion-doped region and couples with a bulk voltage terminal.
This invention also provides a third CMOS structure having a dynamic threshold voltage. The third CMOS structure includes a substrate, a MOS transistor, a first ion-doped region, an isolation layer, a second ion-implanted region and a third ion-implanted region. The substrate has a well region. The MOS transistor has source/drain regions and a gate terminal. The source/drain regions are embedded within the well region. The source/drain regions are doped using dopants that differ from the well. The gate terminal is located above a channel region between the drain region and the source region. The first ion-implanted region is within the well. The first ion-implanted region and the drain region are adjacent to each other except for the isolation layer between them. The first ion-implanted region is electrically connected to the gate terminal. The first ion-implanted region, the source region and the drain region are doped with identical types of ions. The second ion-implanted region is also within the well adjacent to the first ion-implanted region. However, the second ion-implanted region contains dopants that differ from the first ion-implanted region. The third ion-implanted region is also within the well but detached from the second ion-implanted region. The third ion-implanted region contains dopants identical to the ones in the first ion-doped region and couples with a bulk voltage terminal. An alternative design of the CMOS structure further includes a fourth ion-implanted region. The fourth ion-implanted region is also within the well between the second and the third ion-implanted region. The fourth ion-implanted region contains dopants identical to the ones inside the second ion-implanted region.
In brief, this invention provides an equivalent circuit containing back-to-back diodes. Utilizing reverse bias saturation current due to a reverse bias voltage as well as the voltage drop provided by the second diode, substrate bias voltage of the CMOS structure can be adjusted. There is no restriction on the voltage applied to the gate terminal and no extra circuit needs to be supplied. Furthermore, the MOS transistor within the CMOS structure can operates under a larger operating current (I
D
) at an identical low threshold voltage. Therefore, functional capacity of the CMOS structure greatly improves.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5691557 (1997-11-01), Watanabe
patent: 6147386 (2000-11-01), Horiuchi
patent: 5-21737 (1993-01-01), None

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