CMOS structure with FETS having isolated wells with merged deple

Details CMOS structure with FETS having isolated wells with merged deple CMOS structure with FETS having isolated wells with merged deple

1996-05-22

1998-03-24

Monin, Donald

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257375, 257376, 257510, H01L 2702, H01L 21265

Patent

active

057316198

ABSTRACT:
A CMOS integrated circuit with field isolation including an NFET(s) having an isolated P-well, wherein the isolated P-well is adjusted so that it does not extend below the field isolation (e.g., STI) and the width and doping of the P-well and an underlying buried N-well is adjusted so that the depletion regions of the source/drain (S-D) diode and also the well-diode just meet (merge) without overlap in the P-well. The semiconductor device obtains bipolar effect and reduced junction capacitance in a bulk single-crystal technology. A method for fabricating the semiconductor device if also provided.

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Hayden, et al., IEEE Trans. Electron Devices, vol. 41, No. 12, Dec. 1994, pp. 2318-2325.

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