CMOS structure with parasitic channel prevention

Details CMOS structure with parasitic channel prevention CMOS structure with parasitic channel prevention

1993-02-25

1995-10-31

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257374, 257507, 257509, 257630, H01L 2702, H01L 21225, H01L 2906

Patent

active

054632382

ABSTRACT:
A semiconductor device comprises a complementary MOS transistor integrated circuit formed in a semiconductor single crystal silicon disposed on an electrically insulating layer. A thickness of the single crystal silicon in a region in which an N-type MOS transistor is formed is made thicker than the thickness in a region in which a P-type MOS transistor is formed. By this structure, the bottoms of the source region and the drain region of the N-type transistor are separated from the electrically insulating layer by a predetermined distance. The separation of the source region and the drain region from the electrically insulating layer is effective to prevent a parasitic channel from forming, thereby reducing leakage current and making the semiconductor device more efficient.

REFERENCES:
patent: 3783052 (1974-01-01), Fisher
patent: 4725875 (1988-02-01), Hsueh
patent: 4753896 (1988-06-01), Matloubian
patent: 4816893 (1989-03-01), Mayer et al.
patent: 4819052 (1989-04-01), Hutter
patent: 5081062 (1992-01-01), Vasudev et al.
patent: 5164803 (1992-11-01), Ozaki et al.

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