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Buried structure SRAM cell and methods for fabrication

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
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Compact memory circuit

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate

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Compact SRAM cell incorporating refractory...

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell – With passive components
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Compact SRAM cell with FinFET

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
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Cross-diffusion resistant dual-polycide semiconductor...

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
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Drain off-set for pull down transistor for low leakage SRAM's

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Patent

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Dual port memory core cell architecture with matched bit...

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
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FET channel having a strained lattice structure along...

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
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Field effect device with polycrystalline silicon channel

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Patent

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FinFET-based SRAM cell

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
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Full CMOS SRAM cell

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
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Full CMOS SRAM cell

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
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Layout for SRAM structure

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell – With passive components
Patent

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Line layout structure of semiconductor memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate

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Memory cell having conductive sill

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
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Memory cell with capacitance for single event upset protection

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell – With passive components
Patent

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Polycide/poly diode SRAM load

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell – With passive components
Patent

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Scalable two transistor memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate

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Scalable two transistor memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate

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Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
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