Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate
1999-05-06
2001-09-04
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Fet configuration adapted for use as static memory cell
C257S904000, C257S206000, C257S207000, C257S210000
Reexamination Certificate
active
06285088
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor integrated circuits, and more specifically to memory integrated circuits.
BACKGROUND OF THE INVENTION
Memory circuits typically comprise an extremely densely packed array of storage elements or cells: capacitors in dynamic RAMs and cross-coupled inverters in static RAMs. Much effort has been aimed at reducing the dimensions of each of these storage cells to allow ever greater memory capacity for a given amount of semiconductor die space. As the dimensions of the cell components decrease, the effects of the parasitic resistances increase. This is in part due to the relatively enormous lengths of the wordlines and bitlines as compared to the memory cell dimensions. For example, as wordlines are made narrower to allow placement within the memory cell, the resistance of the lines increase. The increased resistance makes the time constant of the line unacceptably high, and a high time constant results in slow memory access times. A solution to this problem has involved tying or strapping the local wordline (typically comprising polycrystalline silicon) to an upper-level metal bus to produce an overall lower wordline resistance. In this approach the local poly wordline is strapped to the metal bus every eight, sixteen, thirty-two or more memory cells, depending upon the access time requirements of the circuit. A drawback of the wordline strap is that typically in prior art designs no space existed within a memory cell for the strap. Consequently, the periodic placement of memory cells was interrupted every eight, sixteen, thirty-two, or more cells to allow space for a strap.
An additional reason for the strap space between blocks in SRAMs is to allow contact for the bias voltage (Vdd) to the n-type well region in which the p-channel MOS transistors of the SRAM cell are formed. Similarly, the strap space allows contact between the Vss bus (typically tied to a reference potential or electrical ground) and the p-type substrate or well. Periodic placement of these contacts within the cell array helps prevent latchup and ensure proper circuit operation.
FIG. 1
is a schematic representation of a prior art SRAM circuit. Two groups of storage cells
100
are separated by a strap column
102
in which a polycrystalline silicon (“poly”) wordline
104
is connected or strapped to metal wordline bus
106
at a point
108
within the strap column. In addition, Vdd bus
110
is strapped to element
112
, which represents the common n-type doped region or well in which the p-channel MOS transistors of cells
100
are formed. Similarly, Vss bus
114
is strapped to element
116
, which represents the common p-type substrate in which the n-channel MOS transistors of cells
100
are formed. Note that each of these strap connections is replicated for each row of cells
100
. Each cell column is bounded by bitlines and complementary bitlines
120
, and is coupled to a bitline and complementary bitline by pass or access transistors
122
.
FIG. 2
is a schematic diagram of a typical prior art memory cell such as is shown in
FIG. 1
as element
100
. The cell is made up of cross-coupled inverters
200
. Each inverter
200
includes a p-channel pull-up MOS transistor
202
and an n-channel pull-down MOS transistor
204
. Terminals
206
represent the common n-type doped well in which the p-channel transistors are formed. Similarly, terminals
208
represent the p-type substrate, or in the case of a twin-well process, the p-type well, in which the n-channel MOS transistors are formed.
FIG. 3
is a prior art layout (exclusive of the metal interconnections) of two storage cells separated by a strap column. Within each cell, p-channel transistors are formed within an n-type well region
300
. The p-channel transistors have p-type source contacts
301
and drain contacts
302
formed in moat region
304
within n-well
300
. The moat regions are bounded by field oxide. Poly gate structures
306
extend over the moat and field oxide regions. The channel for the p-channel transistor is formed in the moat region
304
between the source and drain contacts
301
and
302
. The conductive state of the channel is controlled through application of an appropriate voltage on the gate
306
. Similarly, the n-channel transistors have n-type source contacts
319
and drain contacts
320
formed in moat region
322
, which is formed in the p-type substrate
324
. As shown in the schematic diagram of
FIG. 2
, the gates of the p-channel and n-channel transistors comprising an inverter are connected. Thus the gate poly
306
extends over both moats
304
and
322
. Note also that with one additional source/drain contact
326
, the pass transistor that couples the cell to the bitline is also formed in moat
322
. Poly wordline
328
forms the gate of the pass transistors.
The wordline is widened at a point
350
in the strap column to facilitate contact between the poly local wordline and a wordline bus formed subsequently in an upper level metal interconnect layer. The strap column also contains an n-type ohmic contact
352
to the n-type well
300
and a p-type ohmic contact
354
to the p-type substrate. The contacts
352
and
354
are connected to the Vdd and Vss buses, respectively, that are formed subsequently in an upper level metal interconnect layer. The dummy poly gate structure
356
in the strap column is used to compensate for optical proximity effects that would otherwise influence the gate lengths in the transistors adjacent the strap column. The gate structure
356
physically emulates the gate structure
306
that would be adjacent a cell within the array away from the strap column. The gate structure
356
is typically coupled to either the Vss or Vdd bus.
The penalty for the inclusion of the strap column shown in
FIG. 3
is approximately 4.4% in a design that employs strap columns every sixteen memory cells. A reduction of this penalty would allow more storage cells for a given die area, and more integrated circuits per silicon wafer. Thus, there is a need in the industry for a more compact arrangement.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the invention, there is disclosed an integrated circuit having a memory cell array in which the strapping of cell components is accomplished within a memory cell. This approach consumes less semiconductor die space than the prior art method of strapping cell components in an area between cells.
REFERENCES:
patent: 4692783 (1987-09-01), Monma et al.
patent: 5452245 (1995-09-01), Hickman et al.
patent: 5923060 (1999-07-01), Gheewala
patent: 5932900 (1999-08-01), Lin et al.
patent: 6066866 (2000-05-01), Omori
Brady III Wade James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tran Minh Loan
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