Scalable two transistor memory device

Details Scalable two transistor memory device Scalable two transistor memory device

2003-01-16

2004-03-23

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

C257S316000, C365S185050, C365S185100

Reexamination Certificate

active

06710465

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally directed to semiconductor devices and, more particularly, to the structure of a new planar small dimensional memory cell array and its addressing circuitry.
2. Description of Related Art
DRAM semiconductor devices have an advantage of a possible higher integration density as compared to other memory devices such as SRAM semiconductor devices, but DRAM semiconductor devices cannot maintain a decreasing stored charge, as required by scaling, due to leakage current from memory cells, internal noise, and soft errors caused by incident alpha particles. Therefore, the memory cells of such devices require constant refreshing in order to maintain data stored in the memory cells. Thus, power consumption is large even in stand-by mode.
Flash memory devices or EEPROM devices, on the other hand, have a merit in that there is no need to refresh the memory cells in order to maintain data stored in the memory cells. However, a primary drawback of flash memory devices is that it is difficult to improve its relative slow access time because it takes a relatively long time to program the memory cells. Moreover, a high voltage is necessary to program (write) or erase memory cells of flash memory devices. The high electric field applied during erase/write cycles degrades the SiO
2
tunneling barrier to the floating gate over a predetermined number (typically about 10
5
) of erase/write cycles and, as a result, limits the operational life of the memory device.
Thus, there is a need for a novel memory cell device that combines the advantages of DRAM and flash memory. In other words, there is a need for a semiconductor memory device having memory cells that allow scalable memory charge relative to cell density of the device with long-term retention, low voltage, high speed, and highly reliable operational characteristics. One such novel memory cell, which can be named as a Scalable Two-Transistor Memory cell, has been proposed by Nakazato et al. (refer to IEDM 97, pp. 179-182 and U.S. Pat. No. 5,952,692). Nakazato et al. referred to their device as a Planar Localized Electron Device Memory (PLEDM) cell. This memory cell has non-volatile, high-speed, very low-power dissipation, and high cell density characteristics. It also has an isolated memory node, which provides immunity against soft errors, a gain property, which provides a large S/N ratio. It is a quantum tunneling device working at room temperature with no hot carrier degradation effects, and can be fabricated by existing silicon processing technology.
FIG.
1
(
a
) is a cross-sectional view and FIG.
1
(
b
) is a simple schematic diagram of a typical Scalable Two-Transistor Memory (hereinafter referred to as STTM) cell. The STTM cell comprises a sensing (bottom) transistor (
1
), which is also known as a read or an access transistor; and a programming (top) transistor (
2
), which is also known as a write transistor. As shown in FIG.
1
(
c
), the programming (top) transistor is a vertical double wall gated MOSFET with a multiple tunnel junction barrier (
4
) between the source and the drain. The sensing (bottom) transistor is basically a conventional MOSFET consisting of a floating gate (
6
) (also functioning as a storage node of the memory cell), a drain (
7
) (functioning as a sense line, S; corresponding to a bit line) and a source (
8
) (functioning as a ground line, G; at a ground or a specific potential). As shown in FIG.
1
(
d
), in an STTM cell, the programming (top) transistor (
9
) is stacked on the gate (
6
) of the sensing (bottom) transistor. The storage node (
6
) (floating gate of the sensing or bottom transistor) also functions as the drain region (
10
) of the programming (top) transistor. As shown in FIG.
1
(
d
) and FIG.
1
(
e
), the control gate (
11
), formed over the sidewalls of the barrier structure (
4
) and the storage node (
6
), functions as a control gate line X (which is also known as the write line or word line). The programming (top) transistor's source region (
12
) functions as a data line Y. The MTJ barrier structure is formed by alternatively and sequentially depositing an insulating layer (
13
) and a semiconductor layer (
14
).
In the write mode, a data voltage is applied to the data line Y (
12
) and a write voltage (i.e., program voltage) is applied to the write (or word or control gate) line X (
11
). Therefore, barrier height between the Y line (
12
) and the storage node (
6
) is reduced, and tunneling current flows through the insulating layer. As a result, charges (electrons or holes) may be stored in the storage node (
6
). These stored charges change the threshold voltage of the sensing (bottom) transistor (
1
). For example, in the event that the electrons are stored in the storage node (
6
) and the sensing (bottom) transistor (
1
) is an NMOS transistor, the threshold voltage of the sensing (bottom) transistor (
1
) is increased towards the positive voltage. In a STTM cell, the write operation can be achieved with a low write voltage, as compared to a flash memory device. This is because in a STTM cell, the charge flow into the storage node is controlled by write (or word or control gate) line X (
11
) as well as the data line Y (
12
).
In order to read (sense) the data stored in a STTM cell, a read voltage is applied to the write (or word or control gate) line X (
11
) and an appropriate voltage is applied to the ground line G (
8
). Next, a sense amplifier (not shown) detects the current that flows through the sense line S (
7
). In this case, in the event that the threshold voltage of the sensing (bottom) transistor (
1
) is higher than the read voltage, the sense line current may not flow. If, however, the threshold voltage of the sensing (bottom) transistor (
1
) is lower than the read voltage, the sense line current may flow.
In the above STTM cell, the storage node (
6
) is completely surrounded by insulating material (i.e., completely floated) unlike the storage node of DRAM cell. Thus, in the event that the write voltage is much higher than the read voltage, there is no need to refresh the memory cells. Alternatively, the write (or word or control gate) line can be separated into two write lines with the sensing transistor controlled by a first write line and the programming transistor controlled by a second write line. In this case, even though the write voltage approximates the read voltage, the programming (top) transistor (
2
) is not turned on during the read operation. Accordingly, it is not required to refresh the memory cell regardless of the difference between the write voltage and the read voltage.
FIG. 2
is a possible equivalent circuit diagram of a cell array region in STTM (also called PLEDM). The circuit symbol used for the STTM cell in FIG.
2
and other circuit diagrams later is shown in FIG.
1
(
f
). Referring to
FIG. 2
, a plurality of parallel word lines (WL
1
to WL
5
) are arranged in rows parallel to an x-axis of the STTM cell array. Each of the word lines is electrically connected to the sidewall control gates X (
11
) of the memory cells, which are arrayed in a row direction. Also, a plurality of parallel data lines (DL
1
to DL
3
) are arranged in columns parallel to a y-axis of the STTM cell array. Each of the data lines is electrically connected to the upper nodes of the MTJs Ys (
12
) of the memory cells, which are arrayed in a column direction. The upper nodes of the MTJs (
12
) are also the source terminals of the programming transistors (
2
). As shown in
FIG. 2
, a plurality of parallel bit lines (BL
1
to BL
3
) are also disposed in a column direction in-between the plurality of data lines. Each of the bit lines is electrically connected to the source (
8
) or drain (
7
) regions (S or G in
FIG. 1
) of the sensing (bottom) transistors (
1
) of the memory cells, which are arrayed in a column direction.
As explained above, a unit STTM cell is operated by three control lines: the write (or word or control gate) line (
11
), the bit line (
7
or
8
) a

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