Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell
Reexamination Certificate
2001-08-31
2003-06-24
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Fet configuration adapted for use as static memory cell
C257S904000, C257S357000, C257S358000, C257S359000, C438S157000, C438S153000, C438S154000
Reexamination Certificate
active
06583518
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuits, and more specifically, to a structure and a method for forming a dual-polycide semiconductor structure in an integrated circuit.
BACKGROUND OF THE INVENTION
It is generally accepted that it is desirable to have integrated circuits that are smaller and more power efficient. This is true with respect to many semiconductor devices. For example, with memory devices, having smaller memory cell sizes allows for greater memory density, and consequently, storage of more data in a similar sized device. Similarly, microprocessors having greater transistor density, that is, a smaller transistor feature size, generally have more computing power available. Thus, because of the advantages provided by smaller semiconductor devices, a significant amount of resources have been directed to developing fabrication methods, semiconductor structures, and fabrication and processing equipment to construct smaller devices.
In an effort to minimize the size of a semiconductor structure and reduce the number of processing steps, such as in a static random access memory (SRAM) cell, dual-polycide gate structures having a first portion doped with n-type impurities and second portion doped with p-type impurities are used for the gates of the transistors of the memory cells. Dual-polycide gate structures enable the gates of a CMOS inverter to be formed without performing the processing steps typically required in forming each of the gates of the NMOS and PMOS transistors separately. Moreover, using one polycide structure to form the gates for both the NMOS and PMOS transistors of a CMOS inverter requires less space than having two physically separate gates.
A schematic drawing of a conventional 6T SRAM cell is provided in
FIG. 1
a
, and an example of a mask layout for the 6T SRAM cell is provided in
FIG. 1
b
. As the cross-sectional view of
FIG. 1
c
illustrates, a dual-polycide gate
100
includes a polysilicon layer
110
having a first region
112
doped with n-type impurities and a second region
114
doped with p-type impurities. The gate
100
further includes a silicide strap layer
116
, typically formed from tungsten silicide, that provides a relatively low resistance current path between the first region
112
and the second region
114
. Without the silicide strap layer
116
, the junction between the first and second regions
112
and
114
would behave like a pn-diode, which would be unacceptable in the present application.
A problem, however, with using dual-polycide gate structures, such as the one illustrated in
FIG. 1
c
, is cross-diffusion of dopants between the first and second regions
112
and
114
through the silicide strap layer
116
. It is well known that certain dopants, such as Arsenic, move relatively easily in silicides, such as tungsten silicide. For example, arsenic from the n-poly of the first region
112
migrates into the silicide strap layer
116
and cross-diffuses into the p-poly of the second region
114
. Cross-diffusion causes polysilicon depletion, that is, the polysilicon no longer behaves like metal electrodes. This consequently leads to adverse effects such as gate threshold voltage shift and lower drive capability.
One approach that has been taken to address the issues of cross-diffusion in a polycide gate has been to form separate gates for the different transistors. Physically separating the gates of the different transistors assures that cross-diffusion of dopants cannot take place. This approach typically requires that separate contacts are formed to electrically connect to each of the gates. However, as previously mentioned, increasing the memory cell size to accommodate the additional contacts is typically undesirable, and in some instances, the memory cell design rule limits may not allow for the use of separate contacts. Therefore, there is a need for a dual-polycide semiconductor structure and a method that reduces cross-diffusion of dopants across the dopant boundary.
SUMMARY OF THE INVENTION
Embodiments of the present invention are directed to a dual-polycide semiconductor structure and method for forming the same having reduced dopant cross-diffusion. In a semiconductor structure that includes a polysilicon layer having a first region that is doped with a first dopant and a second region adjoining the first region at an interface that is doped with a second dopant, embodiments of the present invention include forming a conductive layer over the polysilicon layer that overlaps the interface, and then removing a portion of the conductive layer to form a region of discontinuity located at a minimum distance away from the interface. Thus, the conductive layer formed over the polysilicon gate overlaps the interface to provide a low resistance current path between the first and second regions of the polysilicon gate, but also includes a region of discontinuity to reduce dopant cross-diffusion from one region to the other.
REFERENCES:
patent: 6118158 (2000-09-01), Kim
patent: 6333527 (2001-12-01), Kim
patent: 6404023 (2002-06-01), Mori et al.
Abbott Todd R.
Cho Chih-Chen
Trivedi Jigish D.
Wang Zhongze
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Tran Long
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