Drain off-set for pull down transistor for low leakage SRAM's

Details Drain off-set for pull down transistor for low leakage SRAM's Drain off-set for pull down transistor for low leakage SRAM's

1996-10-09

1998-05-26

Whitehead, Carl W.

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

257904, H01L 2711

Patent

active

057570833

ABSTRACT:
The pull down transistor of a static SRAM semiconductor device is formed with oxide and polysilicon regions formed on a doped silicon substrate. A masking area is formed over the drain side of the polysilicon and the areas of the drain region proximal to the gate in the silicon and oxide layers below. N+ dopant is implanted into the unmasked areas of said substrate about the polysilicon region with the drain doping offset by the resist overlying the proximal portion of the drain region. A spacer is formed by chemical vapor deposition about the polysilicon region. Next an N- implantation follows with the offset provided by the spacers about the polysilicon region.

REFERENCES:
patent: 4258378 (1981-03-01), Wall
patent: 4737828 (1988-04-01), Brown
patent: 5254866 (1993-10-01), Ogoh
patent: 5317197 (1994-05-01), Roberts
"A 23-ns4-Mb CMOS SRAM with 0.2-.mu.A Standby Current" by K. Sasaki et al. Pub in IEEE Journal of Solid State Circuits, vol. 25 No. 5 Oct. 1990 pp. 1075-1080.
"A Polysilicon Transistor Technology for Large Capacity SRAM" by S. Ikeda et al, IEDM 90-469-472.
A 5.9 .mu.m.sup.2 Super Low Power SRAM Cell Using a New Phase-Shift Lithography by T. Yawauka et al, IEDM 90-477-480.

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