Polycide/poly diode SRAM load

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell – With passive components

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Details

256536, 256538, 256903, 365175, H01L 2711, H01L 2900, G11C 1136

Patent

active

058567089

ABSTRACT:
A method of manufacturing an SRAM cell with polysilicon diode loads using standard logic technology processing. A P+ polysilicon area and an N+ polysilicon are forms a lateral PN junction. In standard logic technology processing the lateral PN junction is shorted out. In the present invention the lateral PN junction is allowed to function as a polysilicon diode load and an ancilliary lateral PN junction is shorted using a polycide cap layer.

REFERENCES:
patent: 5021849 (1991-06-01), Pfiester et al.
patent: 5135888 (1992-08-01), Chan et al.
patent: 5198382 (1993-03-01), Campbell et al.
patent: 5313087 (1994-05-01), Chan et al.
patent: 5396454 (1995-03-01), Nowak
patent: 5616946 (1997-04-01), Hsu et al.

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