Memory cell with capacitance for single event upset protection

Active solid-state devices (e.g. – transistors – solid-state diode – Fet configuration adapted for use as static memory cell – With passive components

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Details

257300, 257379, 365154, H01K 2702

Patent

active

052049906

ABSTRACT:
A compact capacitor for use in a small memory cell in high density memories is disclosed. Such a capacitor in the cross-coupling of cross-coupled inverters in the memory cell improves single event upset hardness. The subject capacitor in its preferred embodiment is a MOS capacitor with both n+ and p+ connections to the capacitor channel so as to maintain a relatively high capacitance for both positive and negative capacitor gate voltages.

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"Logic-Family & Memory-Cell Designs Providing abrupt Voltage Transitions & High Noise Margins" Proceedings of the 1987 Bipolar Circuits & Technology Meeting.
"DMSP Dosimetry Data: A Space Measurement and Mapping of Upset Causing Phenomena", E. G. Gussenhower, et al., IEEE Trans. Nuclear Science, vol. NS-34, pp. 1251-1255 (1987).
"AN SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM", H. T. Weaver, et al., IEEE Trans. Nuclear Science, vol. NS-34, pp. 1281-1286 (1987).
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