Corrosion-resistant electrode structure for integrated...
Coupled-cap flip chip BGA package with improved cap design...
Crack resistant scribe line monitor structure and method for...
Crack stop and moisture barrier
Crater prevention technique for semiconductor processing
Cross-fill pattern for metal fill levels, power supply...
Crossbar-array designs and wire addressing methods that...
Crossed power strapped layout for full CMOS circuit design
CSP pin configuration compatible with TSOP pin configuration
CSP Semiconductor device having signal and radiation bump...
CSP semiconductor device having signal and radiation bump...
Cu film deposition equipment of semiconductor device
Cu interconnects with composite barrier layers for...
Cu-A1 combined interconnect system
Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys
Cu/low-k BEOL with nonconcurrent hybrid dielectric interface
Cube wireability enhancement with chip-to-chip alignment and thi
Current crowding reduction technique for flip chip package...
Current crowding reduction technique using selective current...
CuSiN/SiN diffusion barrier for copper in integrated-circuit...