CSP pin configuration compatible with TSOP pin configuration

Details CSP pin configuration compatible with TSOP pin configuration CSP pin configuration compatible with TSOP pin configuration

1999-06-02

2001-06-05

Cunningham, Terry D. (Department: 2816)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S773000, C257S778000, C257S786000, C257S779000

Reexamination Certificate

active

06242812

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a pin configuration in a highly integrated memory chip; and, more particularly, to a CSP (Chip Size Package) pin configuration which is compatible with a TSOP (Thin Small Outline Package) pin configuration.
DESCRIPTION OF THE PRIOR ART
In the case of high-speed operation chips or chips having many I/O pins, it is a recent tendency to adopt new package techniques such as CSP and BGA (Ball Grid Array) for safe operation between. semiconductor circuits and interfacing circuits. Generally, the standards of package types, the number of pins and pin rotation of products related to semiconductor memory are discussed or decided by JEDEC (Joint Electronics Device Engineering Council) under the influence of EIA (Electronic Industries Association) in U.S.A.
FIG. 1
is a top view of a 66-pin configuration of a conventional TSOP chip. As shown in
FIG. 1
, pin configuration of the conventional TSOP chip has two parts. One (left side) of them has 33 pins and the other (right side) of them has 33 pins.
FIG. 2
is a top plane view illustrating CSP 60-pin rotation suggested by EIAJ (Electronics Industry Association Japan), which corresponds to the pin rotation of conventional TSOP 66-pin chip. In the drawing, the reference numeral
10
denotes a die,
20
a ball,
3
CSP left side in which right pins (right side
2
) of TSOP are arranged,
4
CSP right side in which left pins (left side
2
) of TSOP are arranged, respectively.
As shown in
FIGS. 1 and 2
, the left pins in
FIG. 1
are arranged in the right side
4
in FIG.
2
and the right pins in
FIG. 1
are arranged in the left side
3
in FIG.
2
. Also, comparing
FIG. 1
with
FIG. 2
, the VSS and DQ
15
pins in
FIG. 1
are arranged in the first row of left side
3
of FIG.
2
and the DQ
14
and VSSQ pins in
FIG. 1
are arranged in the second row of left side
3
of FIG.
2
.
However, it is easily recognized that pin rotation in the second, fifth and fifteen rows shown in dotted line of
FIG. 2
is different from the conventional TSOP pin rotation (FIG.
1
). That is, odd number pins are arranged in the second column in the second, fifth and fifteen rows, but even number pins are arranged in the first column in other rows. In this pin rotation, there are two routing layers between balls of the second row and the third row and between balls of the fifth row and the sixth row.
According to such CSP pin rotation, dies that are designed and produced for the TSOP cannot be compatible with the CSP and the wiring between balls is relatively difficult. Especially, such a wire structure bringing out a cause of signal interference may make the capacity lowered.
Further, the CSP pin rotation in
FIG. 3
a
is presented by a U.S. company, Micron Technology, Inc. There is no problem of the routing layer in case LOC pad array is single pad array, however, in case chip itself adapts to the double pad array, there is a problem. For example, as shown in
FIG. 3
b
, a pin allocated to the left side should be connected to a die pad allocated on the right of the double pad array. It is impossible for this pin across to be applicable to the practical fabrication.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide the CSP pin rotation which is be compatible with the TSOP pin rotation.
Another object of the present invention is to provide a memory device, of which chip pads simultaneously adapt to CSP and TSOP pin rotations.
In accordance with another aspect of the present invention, there is provided a CSP semiconductor device, comprising: a die pad area formed in the middle of a semiconductor chip; a first ball pad area allocated at a left side of the die pad area, having a ball array having first and second columns; and a second ball pad area allocated at a right side of the die pad area, having a ball array having first and second columns, wherein the first ball pad area includes ball pads which are positioned at a right side of a corresponding TSOP, wherein the second ball pad area includes ball pads which are positioned at a left side of the corresponding TSOP, wherein the first column of the first ball pad area includes even number pins of the corresponding TSOP, which are disposed in order, of lower priority, and the second column of the first ball pad area includes odd number pins of the corresponding TSOP, which are disposed in order of lower priority, and wherein the first column of the second ball pad area includes even number pins of the corresponding TSOP, which are disposed in order of higher priority, and the second column of the second ball pad area includes odd number pins of the TSOE, which are disposed in order of higher priority.
In accordance with another aspect of the present invention, there is provided a CSP semiconductor device, comprising: a die pad area formed in the middle of a semiconductor chip; a first ball pad area allocated at a left side of the die pad area, having a ball array having first and second columns; and a second ball pad area allocated at a right side of the die pad area, having a ball array having first and second columns, wherein the first ball pad area includes ball pads which are positioned at a right side of a corresponding TSOP, wherein the second ball pad area includes ball pads which are positioned at a left side of the corresponding TSOP, wherein the first column of the first ball pad area includes odd number pins of the corresponding TSOP, which are disposed in order of lower priority, and the second column of the first ball pad area includes even number pins of the corresponding TSOP, which are disposed in order of lower priority, and wherein the first column of the second ball pad area includes odd number pins of the corresponding TSOP, which are disposed in order of higher priority, and the second column of the second ball pad area includes even number pins of the TSOP, which are disposed in order of higher priority.
In accordance with further another aspect of the present invention, there is provided a CSP semiconductor device, comprising: a die pad area formed in the middle of a semiconductor chip; and first and second ball pad areas which are respectively formed at left and right sides of the die pad area, wherein the first ball pad areas has first and second ball array columns and the second ball pad areas has third and fourth ball array columns, wherein first ball pads corresponding to pins to be positioned at a right side of TSOP die pads are allotted to the first and second ball array columns of the first ball pad area in this order, wherein TSOP pin numbers of the first ball pads allotted to the first ball array column are higher than those allotted to the second ball array column in the same row, wherein second ball pads corresponding to pins to be positioned at a left side of the TSOP die pads are allotted to the third and fourth ball array columns of the second ball pad area in this order and wherein the TSOP pin numbers of the second ball pads allotted to the third ball array column are higher than those allotted to the fourth ball array column in the same row.
In accordance with still another aspect of the present invention, there is provided a method for arranging pins to a CSP in order for die pads of the semiconductor device to be compatible with a TSOP, the method comprising the steps of: a) allotting first ball pads arranged at a left side of the TSOP to a right side of the CSP, wherein the first ball pads of the TSOP are, in this order, allotted to each row of a first ball array of the CSP; and b) allotting second ball pads arranged at a right side of the TSOP to a left side of the CSP, wherein the second ball pads of the TSOP are, in this order, allotted to each row of a second ball array of the CSP, wherein the first ball array is opposite to the second ball array.


REFERENCES:
patent: 5723903 (1998-03-01), Masuda et al.
patent: 5894107 (1999-04-01), Lee et al.
patent: 5920118 (1999-07-01), Kong
patent: 6013946 (2000-01-01), Lee et al.

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