Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond

Reexamination Certificate

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C257S738000, C257S762000, C257S784000, C228S180220

Reexamination Certificate

active

06515373

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to wire bonding of Cu-Pads with Cu-wires using self-passivating Cu-alloys. The self-passivation layer resulting from the dopant rich Cu-alloy protects the Cu from corrosion and oxidation.
2. Description of Related Art
In the art of wirebonding, the current state of the art is to use Al-pads in combination with conventional Al-wedge or Au-ball bonding. However, the introduction of the Al-pads on top of a Cu based metallization is expensive and necessitates additional process steps.
Further, if contemporary bonding of the Cu-wires on Cu-pads is employed, the exposed Cu layer would be highly susceptible to corrosion and oxidation.
The prior art direct chip attachment with wirebonds on conventional overplated, overcoated copper (Cu) pads is costly because costly platings are required on circuit carriers possessing direct chip attach (DCA) wirebonded integrated circuit (IC) chips and wirebond jumper circuits to perform high yield wirebonding on carriers possessing copper circuits. The IC chips are attached to the circuit carrier with an adhesive or solder chip attach material using heat. A circuit covercoat or solder mask covers the copper circuits. In direct chip attach (DCA) wirebond operations, silicon chips are wirebonded to interconnection pads on circuit carriers that possess a combination of barrier underplatings and noble or seminoble metal overplate finishes or surface coatings. The common layered surface finish metallurgies for circuit carrier wirebonding applications are of a nickel (Ni) underplating coating covered by a surface overplating coating layer of gold (Au), palladium (Pd), or silver (Ag). These layered surface finish treatments inhibit diffusion of underlying copper (Cu) circuit metallization to the surface of the overplate and prevent subsequent oxidation of the wirebond pad surfaces. Considerable oxidation of pad surfaces prior to wirebonding can otherwise result in both inability to wirebond with high yield and deterioration of wirebond interconnection reliability. Use of these overplating treatments on copper pads has been used to provide both high yield and high reliability wirebond interconnections.
These plating treatments are costly, due to precious metal content and strict process controls required on plating bath chemistries. Further, when using electrolytic plating, bussing configurations must be provided to all areas requiring a plating treatment. The bussing compromises more efficient wiring configurations and can also prevent maximum usage of available carrier space in both panel and circuit designs. The electrolytic platings can result in higher circuit piece price costs due to inefficient packing of multi-microprocessor circuit configurations on panelized carrier materials including flexible carrier materials, such as polyimide, polyester, and rigid carrier materials, such as a glass epoxy composite or ceramic, liquid crystal polymer (LCP).
U.S. Pat. No. 5,632,438 disclose a direct chip attachment process for aluminum wirebonding on copper circuitization comprising: passing one integrated circuit chip to a carrier; applying to the carrier an attached integrated circuit chip an aqueous cleaning solution containing citric and oxalic acid based additives; applying to the carrier and attached integrated circuit chip a rinse; and wirebonding on copper circuitization carried by the carrier.
A method for improving bond ability for deep-submicron integrated circuit packages is disclosed in U.S. Pat. No. 6,110,816. The method comprises: providing a semiconductor substrate having a top electrically conducting layer, and an overlying layer covering the top electrically conducting layer, and a photoresist applied to the overlying layer; patterning the photoresist to form an array of submicron size holes; etching openings through the overlying layer to the top electrically conducting layer, and forming a rough textured surface profile in the top electrically conducting layer through the opening of the overlying layer; and depositing a passivation film over the overlying layer and forming wiring pad windows for wire ball bonding.
In the art area of wirebonding of Cu-pads with Cu-wires for making integrated circuits, pure Cu-wire bonded to pure Cu-pads provides the best quality bond and lowest resistance; however, pure Cu does not provide a self-passivation effect, and therefore leaves the Cu at peril to corrosion and oxidation. Accordingly, there is a need in this art to provide Cu-wire bonded on Cu-pads so as to provide good bondability and good bond quality coupled with the capacity of self-passivation so as to enable the copper and integrated circuit formed from this fabrication to achieve self-passivation, and thereby resist corrosion and oxidation.
SUMMARY OF THE INVENTION
One object of the present invention is to provide Cu-wire bonded to Cu-pads in a manner so as to provide good bond quality and low resistance, in which the Cu is characterized by self-passivation.
Another object of the present invention is to provide Cu-wire bonded on Cu-pads in a manner so as to provide good bond quality and low resistance, whereby the Cu-wire bonded on Cu-pads is resistant to corrosion and oxidation due to use of self-passivating Cu-alloys.
A further object of the present invention is to provide Cu-wire bonded on Cu-pads to provide good bond quality and lower resistance, by using Cu-wire and Cu-pads fabricated to 100% out of Cu-alloys, to provide Cu-wire bonded to Cu-pads, where the Cu is resistant to corrosion and oxidation due to use of self-passivating Cu-alloys.
A yet further object of the present invention is to provide, Cu-wire bonded to Cu-pads, in which the wire is either a solid Cu-alloy wire or a bi-layer Cu-wire, with an inner core consisting of the Cu-alloy and the outer core being pure Cu, so as to provide good bondability and bond quality upon bonding the copper wire to Cu-pads, to achieve self-passivation from the Cu-alloy.
A further object yet still of the present invention is to provide Cu-wire bonded to Cu-pads wherein the Cu-wire is a bi-layer and the Cu-pad is a bi-layer (Cu-alloy seed layer+pure Cu-fill) to achieve self-passivation and therefore resistance to corrosion and oxidation.
In accordance with the invention good bondability and good bond quality coupled with resistance to corrosion and oxidation is obtained when wire bonding of Cu-pads with Cu-wires is performed using Cu-alloys (Cu—Al, Cu—Mg, and Cu—Li).


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T. Takewaki et al., Excellent Electro/Stress-Migration-Resistance Surface-Silicide Passivated Giant-Grain Cu-Mg Alloy Interconnect Technology for Giga Scale Integration (GSI), 1995, IEEE, IEDM, pp. 253-256 (10.5.1-.4).*
H. Sirringhaus et al., Self-Passivated Copper Gates for Amorphous Silicon Thin-Film Transistors, Aug. 1997, IEEE, IEEE Electron Device Letters, vol. 18, No. 8, pp. 388-390.

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