Crossed power strapped layout for full CMOS circuit design

Details Crossed power strapped layout for full CMOS circuit design Crossed power strapped layout for full CMOS circuit design

2007-04-10

2007-04-10

Owens, Douglas W. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S753000, C257S779000, C257S784000, C257S760000, C257S750000, C257S690000, C257S774000, C257S775000, C257S776000

Reexamination Certificate

active

11002536

ABSTRACT:
An integrated circuit device and method thereof includes a substrate and a plurality of microelectronic devices. Each of the microelectronics devices includes a patterned feature located over the substrate, wherein the pattern feature comprises at least one electrical contact. The integrated circuit also includes a plurality of interconnect layers for distributing electrical power to the plurality of microelectronic devices. The interconnect layers include a plurality of conductive members associated with each interconnect layer, wherein the members of at least one subsequent interconnect layer straddle members of at least one adjacent interconnect layer. The integrated circuit device further includes a plurality of bond pads connected to at least one of the plurality of members of the interconnect layers.

REFERENCES:
patent: 6180495 (2001-01-01), Wilson et al.
patent: 6417032 (2002-07-01), Liaw
patent: 6479845 (2002-11-01), Chen
patent: 6569723 (2003-05-01), Liaw
patent: 6614091 (2003-09-01), Downey et al.
patent: 6642081 (2003-11-01), Patti
patent: 6989600 (2006-01-01), Kubo et al.

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