Current crowding reduction technique for flip chip package...

Details Current crowding reduction technique for flip chip package... Current crowding reduction technique for flip chip package...

2001-11-27

2003-05-20

Talbott, David L. (Department: 7827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S778000, C257S786000, C438S629000, C438S666000

Reexamination Certificate

active

06566758

ABSTRACT:

BACKGROUND OF INVENTION
A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system.
FIG. 1
shows a typical computer circuit board (
10
) having a microprocessor (
12
), memory (
14
), integrated circuits (
16
) that have various functionalities, and communication paths (
18
), i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components on the circuit board (
10
).
A microprocessor, such as the one shown in
FIG. 2
, is electrically connected to a circuit board via a chip package. A chip package, which houses semiconductor devices in strong, thermally stable, hermetically sealed environments, provides a semiconductor device, e.g., the microprocessor, with electronically connectivity to circuitry external to the semiconductor device.
FIG. 2
shows one prior art type of chip package assembly that involves wire bond connections. The wire bonding process involves mounting a microprocessor (
30
) to a substrate (
32
) with its inactive backside (
34
) down. Wires (not shown) are then bonded between an active side (
36
) of the microprocessor (
30
) and the chip package (not shown).
FIG. 3
shows a more recently developed type of chip package assembly known as “flip-chip” packaging. In flip-chip package technology, a microprocessor (
40
) is mounted onto a chip package (
42
), where the active side of the microprocessor (
40
) is electrically interfaced to the chip package (
42
). Specifically, the microprocessor (
40
) has bumps (
44
) on bond pads (not shown) formed on an active side (
46
) of the microprocessor (
40
), where the bumps (
44
) are used as electrical and mechanical connectors. The microprocessor (
40
) is inverted and bonded to chip package (
42
) by means of the bumps (
44
). Various materials, such as conductive polymers and metals (referred to as “solder bumps”), are commonly used to form the bumps (
44
) on the microprocessor (
40
).
As discussed above with reference to
FIG. 3
, the bumps (
44
) on the microprocessor (
40
) serve as electrical pathways between the components within the microprocessor (
40
) and the chip package (
42
). Within the microprocessor (
40
) itself, an arrangement of conductive pathways and metal layers form a means by which components in the microprocessor (
40
) operatively connect to the bumps (
44
) on the outside of the microprocessor (
40
). To this end,
FIG. 4
a
shows a side view of the microprocessor (
40
). The microprocessor (
40
) has several metal layers, M
1
-M
8
, surrounded by some dielectric material (
48
), e.g., silicon dioxide. The metal layers, M
1
-M
8
, are connected to each other by conductive pathways (
50
) known as “vias.” Vias (
50
) are essentially holes within the dielectric material (
48
) that have been doped with metal ions, e.g., boron ions.
Circuitry (not shown) embedded on a substrate of the microprocessor (
40
) transmit and receive signals via the metal layers, M
1
-M
8
, and the vias (
50
). Signals that need to be transmitted/received to/from components external to the microprocessor (
40
) are propagated through the metal layers, M
1
-M
8
, and vias (
50
) to the top metal layer, M
8
. The top metal layer, M
8
, then transmits/receives signals and power to/from the bumps (
44
) located on the active side of the microprocessor (
40
).
FIG. 4
b
shows a top view of the microprocessor (
40
) shown in
FIG. 4
a
. The top metal layer, M
8
, as shown in
FIG. 4
b
, has a number of parallel regions (
60
). These parallel regions (
60
) alternate between regions connected to V
DD
and regions connected to V
SS
. Such a configuration helps reduce electromagnetic interference. The top metal layer, M
8
, is configured such that it is orthogonal with the metal layer below, M
7
, as shown in
FIG. 4
b
. Further, bumps (
44
) on the top metal layer, M
8
, are arranged in a non-uniform fashion with some areas of the top metal layer, M
8
, having larger numbers of bumps (
44
) than other areas.
FIG. 4
c
shows a section of the microprocessor (
40
) shown in
FIG. 4
b
. Particularly,
FIG. 4
c
shows a particular bump (
44
). The bump (
44
) shown in
FIG. 4
c
is connected to the top metal layer, M
8
. On opposing sides of the bump (
44
), there are vias (
50
) that connect the bump (
44
), the top metal layer, M
8
, and the metal layer below, M
7
.
Vias (
50
) provide current paths across the junction between the bump (
44
) and the top metal layer, M
8
. The part of the top metal layer, M
8
, that makes contact with the bump is known as a “landing pad.” Thus, from the bump (
44
), via the landing pad, current is carried away from the bump (
44
) toward the vias (
50
). Arrows indicating the flow of current from the bump (
44
) to the vias (
50
) are shown for illustration purposes in
FIG. 4
c
. Although the vias (
50
) facilitate current flow, because the vias (
50
) are positioned on only two sides of the bump, there is non-uniform current density at the junction between the bump (
44
) and the top metal layer, M
8
. This non-uniform current density, resulting from the placement of vias (
50
) around the bump (
44
), is known as “current crowding.” In this current crowding phenomenon, there is high current density on the sides of the bump (
44
) that are in close proximity to the vias (
50
) and there is low current density in the rest of the junction between the bump (
44
) and the top metal layer, M
8
. Current crowding is a typically undesirable effect because prolonged exposure to current crowding damages the bump (
44
) and areas of the top metal layer, M
8
, subjected to current crowding.
SUMMARY OF INVENTION
According to one aspect of the present invention, an integrated circuit comprises a landing pad, a bump positioned on and electrically connected to the landing pad, and a plurality of vias positioned uniformly around the bump and electrically connected to the landing pad, where current supplied to the bump is distributed to the vias, and wherein the vias connect the landing pad to a metal layer in the integrated circuit.
According to another aspect, an integrated circuit adapted for use with a flip-chip package comprises a landing pad, a bump positioned on the landing pad, and a plurality of vias positioned uniformly around the bump and electrically connected to the landing pad, where the bump electrically connects the integrated circuit and flip-chip package, where current supplied to the bump from the flip-chip package is distributed to the vias, and where the vias connect the landing pad to a metal later in the integrated circuit.
According to another aspect, a method for uniform current transmission around a bump of an integrated circuit comprises disposing a plurality of vias uniformly around a bump, distributing current supplied to the bump to the vias, and distributing current supplied to the vias to the bump, where the vias are arranged uniformly around the bump, and where the vias connect the bump to a metal layer in the integrated circuit.
According to another aspect, a method for adapting an integrated circuit adapted use with a flip-chip package comprises positioning a bump on a landing pad, positioning a plurality of vias uniformly around the bump, and distributing current supplied to the bump from the flip-chip package to the vias, where the bump electrically connects the integrated circuit and flip-chip package, where the vias are electrically connected to the landing pad, and where the vias connect the landing pad to a metal later in the integrated circuit.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5248903 (1993-09-01), Heim
patent: 5700735 (1997-12-01), Shiue et al.
patent: 5736791 (1998-04-01), Fujiki et al.
patent: 5962919 (1999-10-01), Liang et al.
patent: 6306749 (2001-10-01), Lin
patent: 6448641 (2002-09-01), Ker et al.

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