Cu-A1 combined interconnect system

Details Cu-A1 combined interconnect system Cu-A1 combined interconnect system

1998-12-04

2002-02-12

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S762000, C257S765000

Reexamination Certificate

active

06346745

ABSTRACT:

TECHNICAL FIELD
The present invention relates to semiconductor devices comprising combined copper (Cu) or Cu alloy and aluminum (Al) or Al alloy interconnection patterns. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnect structures.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed interdielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenchs which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor “chips” comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via opening is typically formed by depositing an inter-layer dielectric on a conductive layer comprising at least one conductive pattern, forming an opening in the interdielectric layer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the interdielectric layer is removed by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via opening section in communication with an upper trench section, and filling the opening with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and the distance between interconnects decreases, the RC delay caused by the interconnect wiring increases. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.18 micron and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs. Moreover, as line widths decrease, electrical conductivity and electromigration resistance become increasingly important.
Cu and Cu alloys have received considerable attention as a replacement material for Al in VLSI interconnection metallizations. Cu is relatively inexpensive, easy to process, has a lower resistivity than Al, and has improved electrical properties vis-a-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.
An approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP, as in Tenog, U.S. Pat. No. 5,693,563. However, due to Cu diffusion through the interdielectric layer, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), and silicon nitride (Si
3
N
4
) for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the interdielectric layer, but includes interfaces with other metals as well.
There are additional problems attendant upon conventional methodology in forming a combined interconnect system comprising a Cu or Cu alloy feature electrically connected to an Al or Al alloy feature. For example, in a chip with circuit interconnections comprising a mixture of Cu or Cu alloy features and Al or Al alloy features, such as Cu interconnects and Al vias or Al interconnects and Cu vias, Cu and Al must be isolated by effective barrier material to prevent Kirkendal voiding. Conventional barrier layer materials, such as Ta or TaN have a low nitrogen content, e.g., a nitrogen content less than about 50 at. %, and can not serve as effective diffusion barriers for both Al and Cu. Thus, it is difficult to simultaneously satisfy the requirements of both Cu and Al in forming a combined Cu—Al interconnect structure.
There exists a need for a reliable Cu or Cu alloy-Al or Al alloy combined interconnect structure. There also exists a need for methodology enabling the formation of a reliable Cu or Cu alloy-Al or Al alloy interconnect structure with high electromigration resistance and optimal barrier properties against
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a semiconductor device comprising a reliable Cu or Cu alloy-Al or Al alloy combined interconnect structure having high electromigration resistance and high resistance to Cu and Al diffusion.
Another advantage of the present invention is a method of manufacturing semiconductor device comprising a Cu or Cu alloy-Al or Al alloy combined interconnect structure having high electromigration resistance and high resistance to Cu or Al diffusion.
Additional advantages and other features of the present invention are set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by semiconductor device comprising: an aluminum (Al) or Al alloy feature; a copper (Cu) or Cu alloy feature electrically; and a composite electrically connecting the Al or Al alloy feature to the Cu or Cu alloy feature, the composite comprising: a first layer comprising Ta and Al in contact with a surface of the Al or Al alloy feature; a second layer comprising TaN on the first layer; a third layer comprising TaN having a nitrogen content less than that of the TaN of the second layer, on the second layer; and a fourth layer, comprising Ta or TaN having a nitrogen content less than the TaN of the third layer, on the third layer and in contact with a surface the Cu or Cu alloy feature.
Another aspect of the present invention is a method of manufacturing a semiconductor device, the method comprises forming an aluminum (Al) or Al alloy feature; forming a composite comprising; a first layer comprising Ta in contact with the surface of the Al or Al alloy feature; a second layer

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