Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Patent
1995-01-20
1996-07-02
Limanek, Robert P.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
257686, 257797, 257730, H01L 2565, H01L 23538
Patent
active
055325190
ABSTRACT:
Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.
REFERENCES:
patent: 4151546 (1979-04-01), Kawagai et al.
patent: 4754316 (1988-06-01), Reid
patent: 4764846 (1988-08-01), Go
patent: 4949148 (1990-08-01), Bartelink
patent: 4999311 (1991-03-01), Dzarnoski, Jr.; et al.
patent: 5107586 (1992-04-01), Eichelberger et al.
patent: 5121299 (1992-06-01), Frankeny et al.
patent: 5202754 (1993-04-01), Bertin et al.
patent: 5266833 (1993-11-01), Capps
patent: 5381047 (1995-01-01), Kanno
Bertin Claude L.
Cronin John E.
Perlman David J.
International Business Machines - Corporation
Limanek Robert P.
Williams Alexander Oscar
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