2D charge coupled device memory with acoustic charge transport m
2T dual-port DRAM in a pure logic process with...
2T-1C ferroelectric random access memory and operation...
2T2C signal margin test mode using a defined charge and...
2T2C signal margin test mode using a defined charge exchange...
2T2C signal margin test mode using resistive element
2T2R-1T1R mix mode phase change memory array
3-D memory device for large storage capacity
3-dimensional integrated circuit architecture, structure and...
3-level non-volatile semiconductor memory device and method...
3-parameter switching technique for use in MRAM memory arrays
3-parameter switching technique for use in MRAM memory arrays
3-step write operation nonvolatile semiconductor...
3-transistor OTP ROM using CMOS gate oxide antifuse
3.5 transistor non-volatile memory cell using gate breakdown...
3D chip arrangement including memory manager
3T high density nvDRAM cell
3T1D memory cells using gated diodes and methods of use thereof
4-bit prefetch-type FCRAM having improved data write control...
4N pre-fetch memory data transfer system