Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-09
2003-04-29
Elms, Richard (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S185280, C365S185290
Reexamination Certificate
active
06556481
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to semiconductor memories and in particular to channel erase and program for a semiconductor nonvolatile device such as a one-transistor, NOR-type semiconductor integrated circuit device comprising a flash electrically erasable programmable read only memory (EEPROM).
2. Description of the Related Art
In today's leading flash EEPROM technology, a plurality of one-transistor EEPROM cells has been configured into either NAND-type or NOR-type arrays. For NAND-type cell array, the flash cells' sources and drains are mutually connected in series to save die size for the reason of cost reduction. In contrast, for NOR-type cell array, the cells' drains and sources are connected in parallel to respective bit lines and source lines to achieve high read speed at sacrifice of die size increase. It is well known that the NAND-type cell array suffers no over-erase problem due to its unique array structure allowing no leakage path during read. For one-transistor (non-split gate) NOR-type cell array, the over-erase problem may or may not occur and is fully subject to the choice of erase and program methods. Conventionally, program is performed on the basis of bit-by-bit method but erase is performed collectively on all cells of the block. In either NOR-type or NAND-type flash memory, the entire flash chip is divided into several blocks. Typically, the size of each flash block ranges from 64 Kbits to 512 Kbits. The erase operation is normally performed prior to program operation. In NAND-type flash memory, the erase is performed by block(sector) basis and program is performed by page basis. A page is usually defined as a word line and a block is defined as many word lines which share common bit lines within the same divided block. Although several methods of erase and program operations have been proposed before, in the current NAND-type flash memory, the definition of erase and program operations is unified. The erase operation is to decrease the Vt of the cells that are physically connected to the same erased word line or the word lines in the same block. In contrast, the program operation is to increase Vt of cells of selected erased word line or word lines in the selected block. The non-selected cells in the non-selected word lines in the selected block or the non-selected blocks remain undisturbed.
The following U.S. patents of prior art are directed toward the detailed description of NAND type flash EPROM's.
A) U.S. Pat. No. 6,038,170 (Shiba) is directed toward a nonvolatile memory of a hierarchical bit line structure having hierarchical bit lines which includes a plurality of sub-bit lines.
B) U.S. Pat. No. 5,464,998 (Hayakawa et al.) is directed toward a non-volatile semiconductor memory device including NAND type memory cells arranged in a matrix pattern over a semiconductor substrate.
Up to the present, the definitions of erase and program operation for one-transistor NOR-type flash memory remain inconsistent. Erase could be defined to increase the Vt of the cells and program to decrease the Vt of the cells or vise versa depending on preferable flash technology and its design techniques. The following is a summary of erase and program operations for state of the art one-transistor (non-split-gate) NOR-type flash EEPROM technologies.
1) Fowler-Nordheim (F-N) edge-erase, CHE edge-program, One-Transistor, NOR-type flash EEPROM technology. The typical example is an ETOXTM flash cell. In this prior art, the program is performed on bit-by-bit basis to increase cell's Vt by using CHE (Channel-Hot-Electron) method while erase is performed on block basis to decrease cell's Vt by using FN-tunneling method. The CHE program consumes more than 300 &mgr;A per bit, therefore only a few bits can be programmed at a time by an on-chip charge pump of economic area. Unlike CHE, FN-tunneling erase requires only 10 nA per flash cell so that a big block size of 512 Kb can be erased simultaneously. For 3V or lower Vdd operation, about 4 bits of ETOXTM cells are programmed in state-of-the art design. In the CHE operation, hot electrons are injected into cell's floating gate with an increase in Vt. In contrast, for a FN-tunneling operation, the electrons are extracted out of the floating gate with a decrease in Vt. The erase operation is called edge-erase operation, which is done at the edge of the thin tunnel-oxide between the floating gate and the source junction. In this ETOXTM flash cell, the source junction of N+ is used for erase operation only and is made to be much deeper than the drain junction. The source junction of N+ is surrounded with lightly-doped N-implant to reduce the peak electrical field as generated during erase operation at the tunneling edge. The drain junction is formed with shallow N+, with P+ implanted underneath to enhance the electrical field for CHE program. The ETOXTM cell is made non-symmetrical with respect to source and drain junctions of the cell in terms of cell structure and operating conditions; therefore it is very difficult to be shrunk below 0.18 &mgr;m technology for Ultra-high integrated memory.
The key operating conditions for this technology with a cell made on P-substrate are summarized below:
Source
Gate
Drain
Bulk
a) Erase (edge)
+5 V
−10 V
Floating
0 V
b) Program(channel)
0 V
+10 V
+5 V
0 V
c) Read
0 V
Vdd + &Dgr;V
1 V
0 V
Erase
Program
d) Current/per cell
10 nA
>300 &mgr;A
The drawbacks of this ETOXTM flash cell are: a) low cell scalability caused by an asymmetrical cell structure with deep source junction, b) high program current caused by the CHE program scheme, c) high erase current caused by the edge-FN scheme with large substrate leakage current, d) severe over-erase issue caused by the decrease in the Vt of the cells during erase operation, and e) severe channel punch-through problem in shorter channel length devices caused by edge erase.
The following U.S. patents of prior art are directed toward the detailed description of ETOXTM flash cell operations:
A) U.S. Pat. No. 5,712,815 (Colin et al.) is directed toward An improved programming structure for performing a program operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided.
B) U.S. Pat. No. 5,790,456 (Haddad) is directed toward an improved method for performing channel hot-carrier programming in an array of multiple bits-per-cell Flash EEPROM memory cells in a NOR memory architecture so as to eliminate program disturb during a programming operation.
C) U.S. Pat. No. 6,011,715 (Pasotti et al.) is directed toward a programming method for a nonvolatile memory which includes several steps that are repeated until a final threshold value is obtained.
D) U.S. Pat. No. 5,825,689 (Wakita) is directed toward a nonvolatile semiconductor memory device including a memory cell array in which the threshold voltage of a transistor constituting the memory cell is the ground potential or less, and the source voltage condition is changed by a source potential setting circuit in accordance with a detection result from a data detecting circuit.
2) FN channel-erase, FN edge-program, one-transistor, NOR-type flash EEPROM technology. The representative example of this type flash is an ANDTM flash cell. Unlike ETOXTM technology, the program is performed on bit-by-bit basis to decrease cell's Vt while erase is performed on block basis to increase cell's Vt. This operation eliminates the over-erase problem of the ETOXTM technology. Both erase and program operations use the FN-tunneling method, which consumes only about 10 nA per bit without taking the much greater substrate current into account. Therefore a large number of flash cells within a big block can be programmed and erased simultaneously by on-chip charge pump of economic area. For single low power supply Vdd of 3V or below, as many as 16 Kb ANDTM cells in a block are programmed and erased simultaneously. The erase operation
Hsu Fu-Chang
Lee Peter W.
Tsao Hsing-Ya
Wong Mervyn
Ackerman Stephen B.
Aplus Flash Technology Inc.
Nguyen Hien
Saile George O.
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