3-level non-volatile semiconductor memory device and method...

Details 3-level non-volatile semiconductor memory device and method... 3-level non-volatile semiconductor memory device and method...

2010-07-06

2011-12-27

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Particular read circuit

C365S185140

Reexamination Certificate

active

08085607

ABSTRACT:
A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.

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