Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-11-20
2004-05-04
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S145000, C365S149000
Reexamination Certificate
active
06731554
ABSTRACT:
RELATED APPLICATIONS
The present disclosure is related to the following concurrently filed applications, all of which are to be assigned to infineon Technologies AG and all of which are hereby Incorporated by reference in their entirety into the present disclosure:
“2T2C Signal Margin Test Mode Using Different Pre-Charge Levels for BL and /BL” to Michael Jacob et al., Ser. No. 10/301,547; “2T2C Signal Margin Test Mode Using a Defined Charge and Discharge of BL and/BL” to Hans-Oliver Joachim et al., Ser. No. 10/301,548; and “2T2C Signal Margin Test Mode Using a Defined Charge and Discharge of BL and /BL” to Hans-Oliver Joachim et al., Ser. No. 10/301,529.
FIELD OF THE INVENTION
The present invention relates to the implementation of circuits for testing signal margin in memory cells operating in a 2T2C configuration.
BACKGROUND OF THE INVENTION
In semiconductor memories, reliability issues have become more complicated with increasing memory sizes, smaller feature sizes and lower operating voltages. It has become more Important to understand the cell signal sensing operation, the signal of memory cells and the limiting factors. One particularly important characteristic in reliability determinations of semiconductor memories is the signal margin. In a 2T2C memory cell configuration, the signal margin is a measure of the zero-versus-one signal measured by the sense amplifier. It is particularly useful to be able to measure the signal margin at product level. The results of product-level signal-margin tests can be used to optimize reliability and as well as the sense amplifier design and the bit line architecture to optimize dynamic memory cell readout. Moreover, a product level test sequence for signal margin can help ensure full product functionality over the entire component lifetime taking all aging effects into account.
Among the more recent semiconductor memories, Ferroelectric Random Access Memories (FeRAMs) have attracted much attention due to their low-voltage and high-speed operation In addition to their non-volatility.
FIG. 1
shows a typical prior art FeRAM memory cell in a 2T2C configuration. The 2T2C configuration utilizes two transistors and two capacitors per bit. The 2T2C configuration is beneficial because it allows for noise cancellation between the transistors. Two storage capacitors (Cferro) are connected to a common plate line (PL) on one side and to a pair of bit lines (BL, /BL) on the other side via two select transistors (TS). The two transistors are selected simultaneously by a common word line (WL). A dedicated bit line capacitance (CBL) is connected to each bit line. This bit line capacitance is required for the read operation of the memory cell. The differential read signal on the bit line pair is evaluated in a connected sense amplifier. The polarization is always maintained in directly opposed states in the two storage capacitors of one 2T2C memory configuration.
The signals on the bit lines during a read access are shown in FIG.
4
.
FIGS. 4-7
of the present disclosure all include a plot of the read signals on BL /BL vs. time. In these plots, one of the lines represents the read signal on BL and one represents the read signal on /BL. Which signal is represented by which of the lines depends on whether the read signal on BL or the read signal on /BL is larger Both bit lines BL and /BL are pre-charged to the same level (e.g. 0V in the figure). Also, shortly before t
0
, the word line WL is activated (here “active” means WL is high for conventional FeRAMs and low for chain FeRAMs). The word line WL is not deactivated until shortly after write-back is finished. At time t
0
the plate is activated and a read signal appears on the bit lines according to the capacitance ratio C
ferro
/C
BL
. The effective capacitance of a ferroelectric capacitor depends on its polarization state prior to the read operation. At time t
1
the full read signals are developed on the two bit lines. At t
2
the sense amplifier is activated and the bit line signals are boosted to the full bit line voltages. At t
3
the sense amplifier is deactivated and the access cycle ends at t
4
.
A good solution for determining signal margin in FeRAM memory cells utilizing a single transistor and capacitor (1T1C) is to sweep the reference bit line voltage. A prior art method for determining signal margin in 2T2C FeRAM memory cells is to shift the bit line level by capacitor coupling. However, this method is unsatisfactory because it requires an additional capacitor.
It would therefore be desirable to provide a circuit with a test mode section for facilitating a worst case product test sequence for signal margin. It would also be desirable to design such a circuit for use with semiconductor memories in a 2T2C configuration without requiring additional capacitors in the circuit.
SUMMARY OF THE INVENTION
The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. The invention works well with semiconductor memories having a 2T2C configuration.
A first aspect of the present invention proposes in general terms a semiconductor memory test mode configuration, comprising a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor, the first select transistor activated through a connection to a word line; a second capacitor for storing digital data connecting the cell plate line to a second bit line through a second select transistor, the second select transistor activated through a connection to the word line; a sense amplifier connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines; and a resistor connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
Another aspect of the present invention includes a method for testing a semiconductor memory comprising the steps of: activating a cell plate line to produce a read signal on first and second bit lines representing digital data stored by a pair of capacitors connected to the cell plate line through first and second transistors; activating a third transistor connected to the first bit line for a time interval to change the amount of charge on the first bit line by moving charge through a resistor connected through the third transistor to the bit line; activating a sense amplifier connected to the first and second bit lines thereby boosting read signals on the first and second bit lines; and determining a reduced differential read signal on the first and second bit lines due to the changed amount of charge on the first bit line. The method also includes writing write data to the memory, reading read data from the memory, comparing the read data to the written data; and determining the signal margin of the cell when the amount of charge moved through the third transistor is an amount causing a failure of the comparison of the read data with the written data.
REFERENCES:
patent: 6229728 (2001-05-01), Ono et al.
patent: 6522567 (2003-02-01), Iwanari
patent: 2002/0093847 (2002-07-01), Tada
patent: 2003/0185041 (2003-10-01), Takahashi et al.
Jacob Michael
Rehm Nobert
Roehr Thomas
Wohlfahrt Joerg
Fish & Richardson P.C.
Infineon - Technologies AG
Mai Son
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