3-dimensional integrated circuit architecture, structure and...

Details 3-dimensional integrated circuit architecture, structure and... 3-dimensional integrated circuit architecture, structure and...

2006-03-31

2008-08-05

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Format or disposition of elements

C365S052000, C365S185270

Reexamination Certificate

active

07408798

ABSTRACT:
An integrated circuit design, structure and method for fabrication Thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

REFERENCES:
patent: 5087585 (1992-02-01), Hayashi
patent: 5426072 (1995-06-01), Finnila
patent: 5877034 (1999-03-01), Ramm et al.
patent: 5998808 (1999-12-01), Matsushita
patent: 6821826 (2004-11-01), Chan et al.

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