3-transistor OTP ROM using CMOS gate oxide antifuse

Static information storage and retrieval – Systems using particular element – Semiconductive

Reexamination Certificate

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C365S096000, C365S225700

Reexamination Certificate

active

06927997

ABSTRACT:
The present invention relates to an OTP ROM using a CMOS gate oxide antifuse. According to an embodiment of the present invention, in an OTP ROM cell having a first input terminal, a second input terminal and a third input terminal, wherein the OTP ROM stores data by means of a voltage applied to the first to third input terminals, the OTP ROM cell includes a cell access transistor having a gate and drain forming the second input terminal and a source forming the first input terminal, wherein the cell access transistor is activated by a voltage applied to between the gate and source, a high-voltage blocking transistor having a gate, a drain and a source connected to the drain of the cell access transistor, wherein the high-voltage blocking transistor allows the current to flow from the drain to the source by means of a bias voltage applied to the gate, thus blocking the high voltage applied to the third input terminal from being directly applied to the cell access transistor, and an antifuse transistor having a gate forming the third input terminal, and source and drain both of which are connected to each other and are then connected to the drain of the high-voltage blocking transistor, wherein a high voltage is applied to the third input terminal and if the cell access transistor is activated, gate oxide is broken and shorted.

REFERENCES:
patent: 5748025 (1998-05-01), Ng et al.
patent: 6191641 (2001-02-01), Devanney
patent: 6650167 (2003-11-01), Benzer et al.
Jinbong Kim and Kwryo Lee, 3-Transister Antifuse OTP ROM Array using Standard CMOS Process, 2003 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 14, 2003, pp. 239-242.

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