Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2005-04-05
2005-04-05
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S145000, C324S765010, C324S762010, C714S718000
Reexamination Certificate
active
06876590
ABSTRACT:
The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.
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Jacob Michael
Joachim Hans-Oliver
Rehm Nobert
Fish & Richardson P.C.
Infineon - Technologies AG
Lebentritt Michael S.
Nguyen N.
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