3.5 transistor non-volatile memory cell using gate breakdown...

Details 3.5 transistor non-volatile memory cell using gate breakdown... 3.5 transistor non-volatile memory cell using gate breakdown...

2007-02-06

2007-02-06

Nguyen, Taun T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185140, C365S185170, C365S185210, C365S185280

Reexamination Certificate

active

11252461

ABSTRACT:
A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.

REFERENCES:
patent: 6243294 (2001-06-01), Rao et al.
patent: 6972986 (2005-12-01), Peng et al.

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