3-D memory device for large storage capacity

Details 3-D memory device for large storage capacity 3-D memory device for large storage capacity

2001-10-31

2003-01-07

Lam, David (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S055000, C365S171000

Reexamination Certificate

active

06504742

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to memory devices. More particularly, the invention relates to 3-dimensional large storage random access memory devices.
BACKGROUND OF THE INVENTION
There is an ever-increasing demand for dense and large storage capacity in devices such as computers, communication equipments, consumer electronics, etc. This has led to great improvements in the storage and performance of data storage devices such as hard disk drives, solid-state memories, etc. In hard disk drives, small form factors in conjunction with great improvement in area density permitted development of high capacity disk drives.
In integrated circuits, the development of multi-chip modules (MCM) and hybrid manufacturing techniques have led to great reduction in size, and in some cases improved performance in the final product. A commonly used MCM configuration for the dynamic random access memories (DRAM) is the single-in-line memory modules (SIMM). Presently, many memory storage devices are limited to a single layer. This is due generally to two factors. First, active circuitry requires silicon as the base material to support the operation of the memory such as reading and writing. To read and write, address decoders, read/write control logic, sense amplifiers, output buffers, multiplexers, and more are included in a memory chip. These are generally referred to as overhead and typically consume 20-30 percent of the physical memory. Preferably, this overhead is kept low so more space is available for memory. Second factor limiting the memory storage device to a single array layer is the power dissipation constraints.
Recently, multiple array memories fabricated on top of complementary metal oxide semiconductor (CMOS) have been proposed. However, such approach requires via(s) for each memory layer so that each memory layer may be individually connected to the active circuitry. This approach may yield a very dense and efficient memory design for a few layers. But as number of layers increases, the number of via(s) increases to the point where it become difficult to route the signals from memory arrays to the CMOS layer and the routing paths become longer such that this design become less efficient, more complex, and the cost increases as well. The vias may be made small to overcome some of the problems. However, smaller vias correspondingly increase the risk of defects and increase the difficulty in alignment. In addition, interconnects between array layers becomes more difficult and complex.
In addition, the yield of the memory devices is relatively low. The low yield is due to the fact that an individual memory layer cannot be sorted and rejected from a stack of layers. To illustrate, if a single memory layer has a probability p(x) of being defective, then it is readily apparent that an MCM memory made of multiple layers has a probability greater than p(x) of having at least one defective layer. Because of the inability to sort and reject defects on an individualized memory layer level, the overall quality of the memory device suffers and, thus, the yield is low.
SUMMARY OF THE INVENTION
In one respect, an exemplary embodiment of a memory array may include a non-silicon based substrate. The memory array may also include a row conductor formed above the non-silicon based substrate and extending in a row direction and a column conductor formed above the non-silicon based substrate and extending in a column direction such that a cross-point is formed at an intersection between the row conductor and the column conductor. In the cross point, a memory cell may be formed. The memory array may further include an array enable circuit connected to enable/disable at least one of the row conductor and the column conductor.
In another respect, an exemplary embodiment of a memory plane may include a non-silicon based substrate and one or more memory arrays formed above the nonsilicon based substrate. Each memory array may include a row conductor extending in a row direction and a column conductor extending in a column direction such that a cross-point is formed at an intersection between the row conductor and the column conductor. Each memory array may also include a memory cell formed in the cross-point, and an array enable circuit connected to enable/disable at least one of the row conductor and the column conductor.
In a further respect, an exemplary embodiment of a memory device may include an active circuit plane, for example CMOS circuit plane, and one or more memory planes formed above the active circuit plane. Each memory plane may include a non-silicon based substrate one or more memory arrays formed above the non-silicon substrate. Each memory array of each memory plane may include a row conductor extending in a row direction and a column conductor extending in a column direction such that a cross-point is formed at an intersection between the row conductor and the column conductor. Each memory array may also include a memory cell formed in the cross-point, and an array enable circuit connected to enable/disable at least one of the row conductor and the column conductor.
In yet another respect, an exemplary embodiment of a method to fabricate a memory device may include forming an active circuit plane and forming one or more memory planes above the active circuit plane. The method may also include forming a non-silicon based substrate for each memory plane. For each memory plane, the may further include forming one or more memory arrays above the non-silicon substrate. In addition, for each memory array, the method may include forming a row conductor extending in a row direction and forming a column conductor extending in a column direction such that a cross-point is formed at an intersection between the row conductor and the column conductor. The method may still further include forming a memory cell in the cross-point and forming an array enable circuit connected to enable/disable at least one of the row conductor and the column conductor for each memory array.
The above-disclosed embodiments of the present invention may be capable of achieving certain aspects. For example, the memory device may be made with stacking multiple planes of memory arrays, with each plane being fabricated individually. This eliminates the need to fabricate vias and thus the relative complexity of the device is reduced. Also, each array may be individually enabled and disabled, for example through an array select line. Thus defective arrays and/or planes may be sorted out prior to completing the device, which results in increased yield and quality. Further, because the memory planes may be made separately from the active circuitry, substrates of the memory planes may be formed from materials other than silicon. Further yet, memory planes without including overheads such as read/write control logic, sense amplifiers, output buffers, and multiplexers may be fabricated, which increases the capacity by enabling more space to be dedicated to memory. Still further, stacking allows very high capacity to be achieved. In addition, the memory may be volatile, non-volatile, random access or one-time programmable.


REFERENCES:
patent: 5481493 (1996-01-01), Bergemont
patent: 6157356 (2000-12-01), Troutman
patent: 6185122 (2001-02-01), Johnson et al.

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