3-parameter switching technique for use in MRAM memory arrays

Details 3-parameter switching technique for use in MRAM memory arrays 3-parameter switching technique for use in MRAM memory arrays

2008-03-25

2008-03-25

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S171000, C365S173000

Reexamination Certificate

active

11379527

ABSTRACT:
Disclosed herein are various embodiments of a 3-parameter switching technique for MRAM memory cells arranged on an MRAM array. The disclosed technique alters the relationship between the disturbance margin and write margin of MRAM arrays to reduce the overall disturbance for the arrays by either enlarging the write margin with respect to the original disturbance margin or enlarging the disturbance margin in view of the original write margin. In either approach, the disclosed 3-parameter switching technique successfully decreases the inadvertent writing of unselected bits.

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