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Random access memory device with columns of redundant memory cel

Static information storage and retrieval – Addressing – Plural blocks or banks
Patent

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Random access memory device with dual charging circuits differen

Static information storage and retrieval – Read/write circuit – Precharge
Patent

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Random access memory device with integral logic capability

Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Patent

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Random access memory device with nibble mode operation

Static information storage and retrieval – Read/write circuit – Simultaneous operations
Patent

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Random access memory device with redundant row decoder for contr

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Random access memory dual word line recovery circuitry

Static information storage and retrieval – Read/write circuit – Precharge
Patent

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Random access memory employing complementary transistor switch (

Static information storage and retrieval – Read/write circuit – For complementary information
Patent

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Random access memory employing read before write for...

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Random access memory employing unclamped complementary transisto

Static information storage and retrieval – Systems using particular element – Flip-flop
Patent

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Random access memory for use in an emulation environment

Static information storage and retrieval – Read/write circuit – Data transfer circuit
Reexamination Certificate

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Random access memory having a flexible array redundancy scheme

Static information storage and retrieval – Read/write circuit – Bad bit
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Random access memory having a read/write address bus and...

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Random access memory having a second input/output port

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent

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Random access memory having an adaptable latency

Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate

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Random access memory having bit selectable mask for memory write

Static information storage and retrieval – Systems using particular element – Flip-flop
Patent

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Random access memory having bit selectable mask for memory write

Static information storage and retrieval – Systems using particular element – Flip-flop
Patent

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Random access memory having burst mode capability and method for

Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Patent

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Random access memory having control circuit for maintaining acti

Static information storage and retrieval – Addressing – Sequential
Patent

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Random access memory having driver for reduced leakage current

Static information storage and retrieval – Powering – Data preservation
Reexamination Certificate

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Random access memory having fast column access

Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate

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