Random access memory device with nibble mode operation

Details Random access memory device with nibble mode operation Random access memory device with nibble mode operation

1988-01-28

1989-10-17

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

3652385, G11C 800

Patent

active

048751898

ABSTRACT:
For improving controllability and simplifying the circuit arrangement, there is disclosed a random access memory device comprising a nibble decoder circuit operative to control nibble switching transistors and a read/write control circuit operative to control read/write switching circuits and data amplifier circuits independent from the nibble decoder circuit, and three data bits read out from memory cell arrays are transferred to the same memory cell arrays when a new data bit is written into the a memory cell of the other memory cell array directly accessed by an external processor, thereby preventing the data bits from destruction.

REFERENCES:
patent: 4719602 (1988-01-01), Hag et al.

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