Random access memory having driver for reduced leakage current

Details Random access memory having driver for reduced leakage current Random access memory having driver for reduced leakage current

2005-06-21

2005-06-21

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Powering

Data preservation

C365S230060, C365S222000

Reexamination Certificate

active

06909660

ABSTRACT:
One embodiment of the present invention provides a random access memory (RAM) including an array of memory cells arrange in a plurality of rows and columns, wherein access of each row is based on a wordline signal, and a wordline circuit. The wordline circuit includes a voltage node receiving a positive voltage from an external power source, a decoding node receiving a decoding signal having a state representative of an idle mode, and a driver circuit providing to at least one of the rows of memory cells a wordline signal based on the decoding signal and forming a current leakage path from the voltage node to a reference node when the decoding signal state indicates the idle mode.

REFERENCES:
patent: 4800332 (1989-01-01), Hutchins
patent: 5914905 (1999-06-01), Hikichi et al.
patent: 6055206 (2000-04-01), Tanizaki et al.
patent: 6236617 (2001-05-01), Hsu et al.
patent: 6269046 (2001-07-01), Lee et al.
patent: 6307805 (2001-10-01), Andersen et al.
patent: 6781915 (2004-08-01), Arimoto et al.

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