Random access memory device with redundant row decoder for contr

Details Random access memory device with redundant row decoder for contr Random access memory device with redundant row decoder for contr

1991-12-19

1994-03-22

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 371 103, G11C 700

Patent

active

052970884

ABSTRACT:
A row of defective memory cells is replaceable with a row of redundant memory cells for rescuing a random access memory device, and a programming circuit discriminates the address assigned to the row of defective memory cells for allowing a redundant row address decoder circuit to drive a redundant word line coupled with the row of redundant memory cells, wherein the programming circuit checks predetermined row address bits selected from all the row address bits to see whether or not the rows of defective memory cells are accessed for producing an output signal, and the redundant row address decoder circuit identifies one of the redundant word lines on the basis of the other row address bit so that the programming circuit is shared between the redundant word lines, thereby decreasing the real estate for the programming circuit.

REFERENCES:
patent: 4691301 (1987-09-01), Anderson
patent: 4935899 (1990-06-01), Morigami

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