Random access memory employing unclamped complementary transisto

Details Random access memory employing unclamped complementary transisto Random access memory employing unclamped complementary transisto

1984-12-17

1987-01-06

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Flip-flop

365156, 365189, 365190, G11C 1140

Patent

active

046352287

ABSTRACT:
A random access read/write memory array utilizing unclamped complementary transistor current switch (CTS) memory cells and having m columns and n rows. Each of the m columns of memory cells connected between the bit lines of a discrete one of m pairs of bit lines. Each of the n rows of memory cells connected between the word line and drain line of a discrete one of n pairs of word-drain lines. N identical write enhancement circuit means for enhancing the write operation of the memory array employing unclamped CTS memory cells. The write enhancement circuit means is preferably a single PN diode, or diode connected transistor, connected across each word/drain pair.

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Martin et al., "Low Leakage Complementary Transistor Switch Cell", IBM TBD, vol. 26, No. 7A, Dec. '83, pp. 3229-3230.
Boudon et al., "Fast Data Access in a CTS Cell Matrix Memory", IBM TBD, vol. 23, No. 3, Aug. 1980, pp. 1077-1078.
"AC Write Scheme for Bipolar Random-Access Memories Using Schottky Coupled Cells" by J. A. Dorler, J. M. Mosley, R. O. Seeger and J. R. Struk, IBM Technical Disclosure Bulletin, vol. 23, No. 11, Apr. 1981, pp. 4960-4962.

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