Random access memory having an adaptable latency

Details Random access memory having an adaptable latency Random access memory having an adaptable latency

2005-11-01

2005-11-01

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C201S045000, C201S045000

Reexamination Certificate

active

06961276

ABSTRACT:
A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for accessing one or more of the memory cells in response thereto. The random access memory circuit further comprises a plurality of sense amplifiers operatively coupled to the memory cells, the sense amplifiers being configurable for determining a logical state of one or more of the memory cells. A controller coupled to at least a portion of the sense amplifiers is configurable for selectively operating in at least one of a first mode and a second mode. In the first mode of operation, the controller enables one of the sense amplifiers corresponding to the input address and disables the sense amplifiers not corresponding to the input address. In the second mode of operation, the controller enables substantially all of the sense amplifiers. The memory circuit advantageously provides an adaptable latency by controlling the mode of operation of the circuit.

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M.D. Powell et al., “Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping,” Proceedings of the 34th International Symposium on Microarchitecture (MICRO), 12 pages, 2001.

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