Random access memory having a second input/output port

Details Random access memory having a second input/output port Random access memory having a second input/output port

1982-06-30

1985-09-10

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365219, G11C 1140

Patent

active

045410755

ABSTRACT:
A semiconductor random access memory is provided having a second asynchronous input/output port. Block transfers of data can be effected to and from the memory using the second input/output port. Memory throughput efficiency is improved permitting functions such as display refresh in a mapped memory display to be accomplished through the second input/output port. Memory bus contention on the primary port is also relieved. The main input/output port is thereby free to receive new data for a higher percentage of available transfer time since refresh data is available at the second input/output port.

REFERENCES:
patent: 3740723 (1973-06-01), Beausoleil et al.
patent: 3898632 (1975-08-01), Spencer, Jr.
64-k Dynamic RAM Speeds Well Beyond the Pack, Electronic Design, Mar. 19, 1981, pp. 221-225.

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