Random access memory having control circuit for maintaining acti

Details Random access memory having control circuit for maintaining acti Random access memory having control circuit for maintaining acti

1992-12-28

1994-11-22

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sequential

365235, 365207, 3652385, 36523003, 36523009, G11C 700

Patent

active

053674952

ABSTRACT:
A MOS memory device operating at high speed which is so constructed as to hold the sense amplifier activating signals SAP and SAN at high potential and at low potential, respectively, even after the completion of a memory access, and keep the sense amplifier 30a in activated state to hold read data from memory cells. This memory device includes a block decoder which designates mutually different cell array blocks synchronized with a row selection signal RAS and a column selection signal CAS so that it is possible at the time of input of the column selection signal CAS to execute write/read operation in page mode that extends over the cell array blocks.

REFERENCES:
patent: 5185720 (1993-02-01), Vaillancourt et al.
patent: 5222047 (1993-06-01), Matsuda et al.
T. A. Rehage and S. E. Stucka, Enhanced programmable memory address registers, IBM Technical Disclosure Bulletin vol. 24 No. 8, Jan. 1982, pp. 4183-4184.
Data Sheet from NEC Data Book, .mu.PD424400 Dymanic CMOS RAM, pp. 6-199-6-203 and 6-210-6-211, 1991.

Affiliated with

Also associated with

Rating

Random access memory having control circuit for maintaining acti does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Random access memory having control circuit for maintaining acti, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Random access memory having control circuit for maintaining acti will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1995552