Random access memory having a flexible array redundancy scheme

Details Random access memory having a flexible array redundancy scheme Random access memory having a flexible array redundancy scheme

1994-11-30

1996-08-06

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36523003, G11C 700

Patent

active

055441130

ABSTRACT:
A wide Input/Output (I/O) Random Access Memory (RAM) with more efficient redundancy. The RAM array may be divided into individual units. Each unit is further divided into subarray blocks (blocks of subarrays). Each subarray or segment is organized by one and includes one spare column and may include spare word lines. When a block is accessed, only half of the segments are accessed. Whenever a segment is accessed, the segment's spare column is not. The spare columns from the unaccessed half block are available for repairing defective columns in the accessed half block. Data from columns in the accessed half and spare columns in the unaccessed half are transferred to Local Data Lines (LDLs) and from LDLs to Master Data Lines (MDLs). Valid data from accessed column lines and from selected spare lines are provided on the MDLS to second sense amplifiers. Defective columns are electrically replaced with spares after the second stage amplifiers. Thus, all of the spare columns in each half of each subarray block are available to replace an equal number of failed columns at any location in any segment in the other half block.

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