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Selected: M

Memory with data latching circuit including a selector

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Memory with dynamic information storage

Static information storage and retrieval – Read/write circuit – Data refresh
Patent

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Memory with high speed reading operation using a switchable...

Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate

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Memory with high speed reading operation using a switchable...

Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate

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Memory with I/O mappable redundant columns

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent

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Memory with improved BIST

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Memory with improved bit line and write data line equalization

Static information storage and retrieval – Read/write circuit – For complementary information
Patent

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Memory with improved reading time

Static information storage and retrieval – Read/write circuit – Precharge
Patent

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Memory with improved write mode to read mode transition

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent

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Memory with independent access and precharge

Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate

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Memory with latched output

Static information storage and retrieval – Read/write circuit – Signals
Patent

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Memory with minimized redundancy access delay

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory with on-chip detection of bit line leaks

Static information storage and retrieval – Read/write circuit – Differential sensing
Patent

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Memory with on-chip detection of bit line leaks

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Patent

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Memory with output control

Static information storage and retrieval – Read/write circuit – Serial read/write
Reexamination Certificate

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Memory with permanent array division capability

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent

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Memory with power supply intercept in redundancy logic

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Memory with read cycle write back

Static information storage and retrieval – Read/write circuit – Particular write circuit
Reexamination Certificate

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Memory with read protected zones

Static information storage and retrieval – Read/write circuit – Signals
Patent

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Memory with reduced sub-threshold leakage current in dynamic...

Static information storage and retrieval – Read/write circuit – Accelerating charge or discharge
Reexamination Certificate

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