Memory with read cycle write back

Details Memory with read cycle write back Memory with read cycle write back

2011-08-30

2011-08-30

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Read/write circuit

Particular write circuit

C365S190000, C365S191000, C365S207000

Reexamination Certificate

active

08009489

ABSTRACT:
A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle.

REFERENCES:
patent: 6208575 (2001-03-01), Proebsting
patent: 7203886 (2007-04-01), Brown et al.
patent: 2002/0136077 (2002-09-01), Spirkl
patent: 2005/0114588 (2005-05-01), Lucker et al.
patent: 2007/0291561 (2007-12-01), Braceras et al.
patent: 2008/0031063 (2008-02-01), Braceras et al.

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