Memory with improved bit line and write data line equalization

Details Memory with improved bit line and write data line equalization Memory with improved bit line and write data line equalization

1989-09-05

1991-08-27

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

For complementary information

365203, 365204, G11C 700, G11C 1140

Patent

active

050439456

ABSTRACT:
A memory for performing read cycles and write cycles has memory cells located at intersections of word lines and complementary bit line pairs. A row decoder receives a row address and drives a word line in response. In the read cycle, a column decoder decodes a column address to couple selected bit line pairs to global data lines for subsequent output. In the write cycle, write global data lines receive input data signals and couple them to selected bit line pairs for storage in memory cells located at intersections of the selected bit line pairs and enabled word lines. After the write cycle, equalization of bit lines is achieved partly by bit line loads coupled to each bit line, and partly by write data line loads located in the column decoder. Because the write data line loads are coupled to the bit lines after column decoding has taken place, the write data line loads can be shared by several bit line pairs. Thus, layout space is saved due to the sharing, and transistors in the write data line load can be made larger to improve the speed of the bit line equalization.

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Ochii et al., "An Ultralow Power 8K.times.8-Bit Full CMOS RAM with a Six Transistor Cell", IEEE Journal of Solid State Circuits, vol. SC-17, No. 5, Oct. 1982, pp. 798-803.

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